Re: [PATCH] cxl: Fix use of phys_to_target_node() outside of init section

[Dan Williams <dan.j.williams@intel.com>]

Robert Richter wrote:
> Hi Dan,
> 
> patch below. I have not included it into v2 of the SRAT/CEDT changes
> as it is cxl specific and can be applied separately.
> 
> Thanks,
> 
> -Robert
> 
> 
> On 18.03.24 14:26:41, Dan Williams wrote:
> > It should also be the case that cxl_acpi needs this:
> > 
> > diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
> > index 67998dbd1d46..1bf25185c35b 100644
> > --- a/drivers/cxl/Kconfig
> > +++ b/drivers/cxl/Kconfig
> > @@ -6,6 +6,7 @@ menuconfig CXL_BUS
> >         select FW_UPLOAD
> >         select PCI_DOE
> >         select FIRMWARE_TABLE
> > +       select NUMA_KEEP_MEMINFO if NUMA
> >         help
> >           CXL is a bus that is electrically compatible with PCI Express, but
> >           layers three protocols on that signalling (CXL.io, CXL.cache, and
> 
> From be5b495980bae41d879909212db02dac0fba978e Mon Sep 17 00:00:00 2001

Hi Robert,

When you send inline patches like this can you remember to include a
scissors line? That way tools like "b4 am" automatically know where to
trim things. So add a line like the following:

-- >8 --

...see "git mailinfo --help" for details.

Also note that if you reply with an updated patch in a series include
the "vX NN/MM" suffix, like "Subject: [PATCH v3 2/3] ..." so that b4 am
knows to perform a "partial reroll".

> From: Robert Richter <rrichter@amd.com>
> Date: Tue, 19 Mar 2024 09:28:33 +0100
> Subject: [PATCH] cxl: Fix use of phys_to_target_node() outside of init section
> 
> The CXL driver uses both functions phys_to_target_node() and
> memory_add_physaddr_to_nid(). The x86 architecture relies on the
> NUMA_KEEP_MEMINFO kernel option to be set. Enable the option for the
> driver accordingly.
> 
> Suggested-by: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> ---
>  drivers/cxl/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
> index 67998dbd1d46..6140b3529a29 100644
> --- a/drivers/cxl/Kconfig
> +++ b/drivers/cxl/Kconfig
> @@ -6,6 +6,7 @@ menuconfig CXL_BUS
>  	select FW_UPLOAD
>  	select PCI_DOE
>  	select FIRMWARE_TABLE
> +	select NUMA_KEEP_MEMINFO if (NUMA && X86)
>  	help
>  	  CXL is a bus that is electrically compatible with PCI Express, but
>  	  layers three protocols on that signalling (CXL.io, CXL.cache, and
> -- 
> 2.39.2
>