Re: [ACPI Code First ECN] Enumerate "Inclusive Linear Address Mode" memory-side caches

[Dan Williams <dan.j.williams@intel.com>]

Jonathan Cameron wrote:
[..]
> > > So should the text say anything about decoder address vs (SRAT / HMAT addressing)
> > > Maybe reasonable to say it's contained and aligned so modulo maths works?
> > > This is a bit odd as HMAT wouldn't typically provide this info, but this addressing
> > > mode already incorporates it sort of...  
> > 
> > SRAT portrays capacity, HMAT portrays cache and address organization.
> > There is no need for bringing CXL decoder concepts into the HMAT.
> 
> Absolutely - avoid any reference to decoders and we are fine.

Well no, because the implications of this addressing mode relative to
CXL decoder settings is the whole reason why "we", Linux CXL community,
are motivated to submit a code-first ECN proposal to explicitly
advertise this addressing mode. The Linux CXL subsystem needs to know
about this addressing mode because of the mismatch between endpoint
decoders and SPA ranges relative to endpoint HPA decode ranges.

Will try to make this point clear because I do not to see a path to
describe the motivation for this ECN without talking about the CXL
problem.