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Mon, 24 Jun 2024 20:51:03 +0000 Date: Mon, 24 Jun 2024 13:51:00 -0700 From: Dan Williams To: Terry Bowman , Dan Williams , , , , , , , , , , , , , , Subject: Re: [RFC PATCH 0/9] Add RAS support for CXL root ports, CXL downstream switch ports, and CXL upstream switch ports Message-ID: <6679dc345fd4c_5639294a5@dwillia2-xfh.jf.intel.com.notmuch> References: <20240617200411.1426554-1-terry.bowman@amd.com> <6675cece52eaf_57ac294ea@dwillia2-xfh.jf.intel.com.notmuch> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: MW4PR03CA0014.namprd03.prod.outlook.com (2603:10b6:303:8f::19) To PH8PR11MB8107.namprd11.prod.outlook.com (2603:10b6:510:256::6) Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8107:EE_|SA2PR11MB4796:EE_ X-MS-Office365-Filtering-Correlation-Id: 891cd948-99ba-4870-2b53-08dc948f5c95 X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|366013|1800799021|376011|7416011|921017; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?cAiy0696ynQIg+s9Hdbjn5Jzq2raJipz9as/c52EX6Slc6G3toWwGwVB+w9X?= =?us-ascii?Q?VSNV2TwsnO97SmsYwptc2tDiv8wuWNHjhXLIGWZkqFCQRfQlmACS7JCYIUCe?= =?us-ascii?Q?GRcHzu4dh7Y3U1rz1N7J9xJOUW5mDJQ7SpTjTMwon9X4JoRaiklgM6cy0gmT?= =?us-ascii?Q?c6oR6RCWL3SzFw/RSApDR+jLW7Do4WD1jB7/L4g+U3KqilsCH1lo48c/kJ61?= =?us-ascii?Q?JHp9zVsVmr9/2r23tmQX5CXpcCi3TOGOosP5EZQeXlsuZiGtHR66VjqCSW+U?= =?us-ascii?Q?YcNW5qfZb672CAsTw/Lfd29OtGmUgAc4thUfLXaRSphD8Yyi5zqX/ECZY0xN?= =?us-ascii?Q?zkCLhGKT2tW7ILGeyPVTaJxem6BPlfGEKrU/DNbTbHJ9DWQeK1qBM1+OFp3z?= =?us-ascii?Q?K7696GWM4GBZV6JW+ilh+1eLhboHYJLtklfJajWn+9lFSRaWJpAw0jnq9INF?= =?us-ascii?Q?Y3hIu+7zIKd2EsZqboEThsdIZyPcyaIgp3yrSZl8gEd7GW3AmK0gnqtfPfna?= =?us-ascii?Q?43nv3wnS//ljEc4Q8ZMKEqIi0KIOK4MJKzVukSBiRQOvyDPmwtKFi35QfsMw?= =?us-ascii?Q?dkPgtETBQNY9yMluuI0C5hhWlQ1gBZZHa6SzBU/XOHOGjNvaMUoRJlhsuaET?= =?us-ascii?Q?9UFS7ND2xeGjh+3hrdHxsu4UHo1tBSTwhbz3km661iSUHiHAitnTjm/Wchxm?= =?us-ascii?Q?fPHScxtEjNrki63wxCbdcxx5Gy85B3Qw1zj0idX/fXQO/3JmCydRGUs4rMeG?= =?us-ascii?Q?IkhIlaNMs/ABQxB6oy1WhhueYop/6h9IDApz9uZdI92Em6E30zOkObXaME3u?= =?us-ascii?Q?k8EQFpPklgRJqKXHznZu6R3ZKJhosDTvK6oezV8YMkNJYX6RHVFZHZfCEEqS?= =?us-ascii?Q?tB9yIJf+ScOZ8BZWZMQdgfHJyiRc91NvsBl2CEfihfiUOG8wm70VwemShvD6?= =?us-ascii?Q?QY0EJh8Pxr1x1Cit6otiGoxui8VlmTctYu+GEOrNQQbpBbF5t+hRoLqLUmfv?= =?us-ascii?Q?yBluVk+7VFWsswRhihvdEv+CulBfYXnl1l7fXrGxkSu1bEwXlN+ydnctRIYp?= =?us-ascii?Q?zKhxhfC66ZYeYpuTgj8DiEqtw6vTXsocI2ERxWvH8IwC09txN+3lLI4zaOgp?= =?us-ascii?Q?bLCPaxeLX33LIccUFWZpXACqNpu9akef/Vdby4ALVAlkckJQxgaF4g5jne7l?= =?us-ascii?Q?+8V/L3a7Rj5hy9UAWdPk4CzLrWDHnV3LsryHEO48mxuq9X9htnOpt0iJkysK?= =?us-ascii?Q?S0lTMSdN4X6rASWfqBUYbNN5RuA4XObr7iCZSvPVTLe+SNgmUho66RKRqVKi?= =?us-ascii?Q?AtQTKoz8MNmHUzG8CNsdXoB1frSqYRmNn3KFCbhTNsu1SsrT3TSBwoZ4wX1g?= =?us-ascii?Q?sme5f4y+q63dWzblgACUVExoV9ktx47wiqDpS2Ll5sWEZpuouwqo0CdfnlXS?= =?us-ascii?Q?pXfAZGDP7AqFYUJoCEeThRRhS4X88a7GEMc9YlHLP8zZb8d939+Z0glLCo7l?= =?us-ascii?Q?W6Qf6amyjQKx8jQdB2RQmvklFUIVkC7h7uatTYXIe5rgehw5lMCrt3hXmlTP?= =?us-ascii?Q?ocGffJ0NkZpkXcyJMHW63wrU+FWoU5BnBhIQIbxfH4qiCOOQ3vzYfSj6KdvX?= =?us-ascii?Q?rg=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 891cd948-99ba-4870-2b53-08dc948f5c95 X-MS-Exchange-CrossTenant-AuthSource: PH8PR11MB8107.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2024 20:51:03.5757 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: XOsupbD3DUdIiHx56LNtjbSNMzVbK0HsB+6+Ma+4hYb6pDiKH1KYnP4e1Ykl7iFBLITYxsYEtWud9rn/gSGvP42/M+MevTdp0NCYoDFZbPo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR11MB4796 X-OriginatorOrg: intel.com Terry Bowman wrote: > Hi Dan, > > I added responses below. > > On 6/21/24 14:04, Dan Williams wrote: > > Terry Bowman wrote: > >> This patchset provides RAS logging for CXL root ports, CXL downstream > >> switch ports, and CXL upstream switch ports. This includes changes to > >> use a portdrv notifier chain to communicate CXL AER/RAS errors to a > >> cxl_pci callback. > >> > >> The first 3 patches prepare for and add an atomic notifier chain to the > >> portdrv driver. The portdrv's notifier chain reports the port device's > >> AER internal errors to the registered callback(s). The preparation changes > >> include a portdrv update to call the uncorrectable handler for PCIe root > >> ports and PCIe downstream switch ports. Also, the AER correctable error > >> (CE) status is made available to the AER CE handler. > >> > >> The next 4 patches are in preparation for adding an atomic notification > >> callback in the cxl_pci driver. This is for receiving AER internal error > >> events from the portdrv notifier chain. Preparation includes adding RAS > >> register block mapping, adding trace functions for logging, and > >> refactoring cxl_pci RAS functions for reuse. > >> > >> The final 2 patches enable the AER internal error interrupts. > > [..] > >> > >> Solutions Considered (1-4): > >> Below are solutions that were considered. Solution #4 is > >> implemented in this patchset. > > [..] > >> 2.) Update the AER driver to call cxl_pci driver's error handler before > >> calling pci_aer_handle_error() > >> > >> This is similar to the existing RCH port error approach in aer.c. > >> In this solution the AER driver searches for a downstream CXL endpoint > >> to 'handle' detected CXL port protocol errors. > >> > >> This is a good solution to consider if the one presented in this patchset > >> is not acceptable. I was initially reluctant to this approach because it > >> adds more CXL coupling to the AER driver. But, I think this solution > >> would technically work. I believe Ming was working towards this > >> solution. > > > > I feel like the coupling is warranted because these things *are* PCIe > > and CXL ports, but it means solving the interrupt distribution problem. > > > > I understand the service driver interrupt issue but it is not clear how it > applies to the CXL port error handling. Can you help me understand how the > interrupt issue affects CXL port AER UIE/CIE handling in the AER driver. Just the case of the AER MSI/-X vector being multiplexed with other CXL functionality on the same device. If the CXL interrupt vector is to be enabled later then it means MSI/-X vector enabling needs to be dynamic. ...but yeah, not a problem now as we are only talking about PCIe AER events and not multiplexing yet. I.e. that problem can be solved later. > > > >> 3.) Refactor portdrv > >> The portdrv refactoring solution is to change the portdrv service drivers > >> into PCIe auxiliary drivers. With this change the facility drivers can be > >> associated with a PCIe driver instead fixed bound to the portdrv driver. > >> > >> In this case the CXL port functionality would be added either as a CXL > >> auxiliary driver or as a CXL specific port driver > >> (PCI_CLASS_BRIDGE_PCI_NORMAL). > >> > >> This solution has challenges in the interrupt allocation by separate > >> auxiliary drivers and in binding of a specific driver. Binding is > >> currently based on PCIe class and would require extending the binding > >> logic to support multiple drivers for the same class. > >> > >> Jonathan Cameron is working towards this solution by initially solving > >> for the PMU service driver.[1] It is using the auxiliary bus to associate > >> what were service drivers with the portdrv driver. Using a CXL auxiliary > >> for handling CXL port RAS errors would result in RAS logic called from > >> the cxl_pci and CXL auxiliary drivers. This may need a library driver. > > > > I don't think auxiliary bus is a fundamental step forward from pcie > > portdrv, it's just a s/pcie_port_bus_type/auxiliary_bus_type/ rename, > > but with all the same problems around how to distribute interrupt > > services to different interested parties. > > > > So I think notifiers are interesting from the perspective of a software > > hack to enable interrupt distribution. However, given that dynamic MSI-X > > support is within reach I am interested in exploring that path and > > mandating that archs that want to handle CXL protocol errors natively > > need to enable dynamic MSI-X. Otherwise, those platforms should disclaim > > native protocol error handling support via CXL _OSC. > > > > In other words, I expect native dynamic MSI-X support is more > > maintainable in the sense of keeping all the code in one notification > > domain. > > > >> 4.) Using a portdrv notifier chain/callback for CIE/UIE > >> (Implemented in this patchset) > >> > >> This solution uses a portdrv atomic chain notifier and a cxl_pci > >> callback to handle and log CXL port RAS errors. > > > > Oh, I will need to look that the cxl_pci tie in for this, I was > > expecting cxl_pci only gets involved in the RCH case because the port > > and the endpoint are one in the same object. in the VH case I would only > > expect cxl_pci to get involved for its own observed protocol errors, not > > those reported upstream from that endpoint. > > > > The CXL port error handling needs a place to live with few options at the moment. > Where do you want the CXL port error handlers to reside? I need to go understand exactly why cxl_pci is involved in this current proposal, but I was thinking it is probably more natural for cxl_port to have error handlers.