Re: [PATCH] Documentation: CXL Maturity Map

[Dan Williams <dan.j.williams@intel.com>]

Alejandro Lucero Palau wrote:
> Apologies for the late answer.
> 
> 
> RAS is covered but what about how CXL/PCI devices are handled after a 
> slot reset?
> 
> I did expose my concern in that area when discussing the Type2 support 
> patchset, and if I'm not wrong this is not properly supported: nothing 
> for device detachment which should occur before the slot reset, nothing 
> for resume function after the slot reset. This is obviously more 
> important for Type2 devices and maybe not required for Type3.

Circling back to this as I go to post v2...

I think those type-2 RAS aspects are important, but it is not clear that
they are a concern of the CXL core. Endpoint drivers are enabled to get
pre and post reset notification via their registered 'struct
pci_error_handlers' operations. This maturity list is more targeted at
the CXL core infrastructure capabilities and type-2 drivers are going to
have their own localized maturity level.

I do need to go look more closely at your RAS assertions on that set. I
had otherwise been waiting a new posting with the sfc integration.