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From: PJ Waskiewicz <ppwaskie@kernel.org>
To: Alejandro Lucero Palau <alucerop@amd.com>,
	alejandro.lucero-palau@amd.com, 	linux-cxl@vger.kernel.org,
	netdev@vger.kernel.org, dan.j.williams@intel.com,
		edward.cree@amd.com, davem@davemloft.net, kuba@kernel.org,
	pabeni@redhat.com,  edumazet@google.com, dave.jiang@intel.com
Subject: Re: [PATCH v21 00/23] Type2 device basic support
Date: Fri, 21 Nov 2025 17:08:25 -0800	[thread overview]
Message-ID: <6689415773004afd10b3a0035862dd4faaf78021.camel@kernel.org> (raw)
In-Reply-To: <8d8cb631-1d72-436f-ac97-5449ba46ef42@amd.com>

On Fri, 2025-11-21 at 10:40 +0000, Alejandro Lucero Palau wrote:
> 
> On 11/21/25 06:41, PJ Waskiewicz wrote:
> > On Wed, 2025-11-19 at 19:22 +0000, alejandro.lucero-palau@amd.com
> > wrote:
> > 
> > Hi Alejandro,
> > 
> > Sorry it's been a bit since I've been able to comment.  I've been
> > trying to test these patchsets with varying degrees of success. 
> > Still
> > haven't gotten things up and running fully.  One comment below.
> 
> 
> Hi,
> 
> 
> No worries!
> 
> 
> > > From: Alejandro Lucero <alucerop@amd.com>
> > > 
> > > The patchset should be applied on the described base commit then
> > > applying
> > > Terry's v13 about CXL error handling. The first 4 patches come
> > > from
> > > Dan's
> > > for-6.18/cxl-probe-order branch with minor modifications.
> > > 
> > > v21 changes;
> > > 
> > >    patch1-2: v20 patch1 splitted up doing the code move in the
> > > second
> > > 	    patch in v21. (Jonathan)
> > >   
> > >    patch1-4: adding my Signed-off tag along with Dan's
> > > 
> > >    patch5: fix duplication of CXL_NR_PARTITION definition
> > > 
> > >    patch7: dropped the cxl test fixes removing unused function.
> > > It was
> > > 	  sent independently ahead of this version.
> > > 
> > >    patch12: optimization for max free space calculation
> > > (Jonathan)
> > > 
> > >    patch19: optimization for returning on error (Jonathan)
> > I cannot test these v21 patches or the v20 patches for the same
> > reason.
> > I suspect v19 is also affected, but I was stuck on v17 for awhile
> > (b4
> > was really not likely the prereq patches you required to get the
> > tree
> > into a usable state to apply your patchset).
> > 
> > When I build and go to install the kernel mods, depmod fails:
> > 
> > DEPMOD  /lib/modules/6.18.0-rc6+
> > depmod: ERROR: Cycle detected: cxl_core -> cxl_mem -> cxl_port ->
> > cxl_core
> > depmod: ERROR: Cycle detected: cxl_core -> cxl_mem -> cxl_core
> > depmod: ERROR: Found 3 modules in dependency cycles!
> > 
> > I repro'd this on a few different systems, and just finally repro'd
> > this on a box outside of my work network.
> > 
> > This is unusable unfortunately, so I can't test this if I wanted
> > to.
> 
> 
> I have been able to reproduce this, and I think after the changes 
> introduced in patches 2 & 3, we also need this:
> 
> 
> 
> diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
> index 6b871cbbce13..94a3102ce86b 100644
> --- a/drivers/cxl/Kconfig
> +++ b/drivers/cxl/Kconfig
> @@ -1,6 +1,6 @@
>   # SPDX-License-Identifier: GPL-2.0-only
>   menuconfig CXL_BUS
> -       tristate "CXL (Compute Express Link) Devices Support"
> +       bool "CXL (Compute Express Link) Devices Support"
>          depends on PCI
>          select FW_LOADER
>          select FW_UPLOAD
> 
> 
> This changes implies neither CXL_BUS optionally being a module nor
> cxl_mem.
> 
> 
> This should be enough for at least you able to test the patchset.
> 
> 
> If this is agreed, I will send a v22 with it.

This seems reasonable to me to make things work.

I'd definitely want Dave or Dan to weigh in though since this does make
CXL no longer be modular, and it's either built-in or not.  Personally,
if this is the price to pay for the non-asynchronous nature of memdev
creation for a Type2 driver, I'm fine with that.

I'm rebuilding now and will rebase my drivers onto this, and hopefully
be testing again over the weekend.  If things start looking good, I'll
send some Tested-by: and also review more deeply.

Cheers,
-PJ

  reply	other threads:[~2025-11-22  1:08 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-19 19:22 [PATCH v21 00/23] Type2 device basic support alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 01/23] cxl/mem: refactor memdev allocation alejandro.lucero-palau
2025-11-20 18:08   ` Jonathan Cameron
2025-11-20 18:27     ` Alejandro Lucero Palau
2025-11-21 12:06       ` Jonathan Cameron
2025-11-21 13:46         ` Alejandro Lucero Palau
2025-11-20 20:27   ` Koralahalli Channabasappa, Smita
2025-11-21 13:41     ` Alejandro Lucero Palau
2025-12-02  2:52   ` dan.j.williams
2025-12-02  4:58     ` dan.j.williams
2025-12-02  8:47     ` Alejandro Lucero Palau
2025-11-19 19:22 ` [PATCH v21 02/23] cxl/mem: Arrange for always-synchronous memdev attach alejandro.lucero-palau
2025-12-02  5:03   ` dan.j.williams
2025-11-19 19:22 ` [PATCH v21 03/23] cxl/port: Arrange for always synchronous endpoint attach alejandro.lucero-palau
2025-12-02  5:08   ` dan.j.williams
2025-11-19 19:22 ` [PATCH v21 04/23] cxl/mem: Introduce a memdev creation ->probe() operation alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 05/23] cxl: Add type2 device basic support alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 06/23] sfc: add cxl support alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 07/23] cxl: Move pci generic code alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 08/23] cxl/sfc: Map cxl component regs alejandro.lucero-palau
2025-11-21  6:54   ` PJ Waskiewicz
2025-11-21 11:01     ` Alejandro Lucero Palau
2025-11-22  1:11       ` PJ Waskiewicz
2025-11-19 19:22 ` [PATCH v21 09/23] cxl/sfc: Initialize dpa without a mailbox alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 10/23] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 11/23] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 12/23] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 13/23] sfc: get root decoder alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 14/23] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 15/23] sfc: get endpoint decoder alejandro.lucero-palau
2025-11-26  1:27   ` PJ Waskiewicz
2025-11-26  9:09     ` Alejandro Lucero Palau
2025-11-26 18:35       ` PJ Waskiewicz
2025-11-27  9:08         ` Alejandro Lucero Palau
2025-12-02  8:49           ` PJ Waskiewicz
2025-12-02  9:09             ` Alejandro Lucero Palau
2025-12-02 16:35         ` Dave Jiang
2025-11-19 19:22 ` [PATCH v21 16/23] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 17/23] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 18/23] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 19/23] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 20/23] cxl: Avoid dax creation for accelerators alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 21/23] sfc: create cxl region alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 22/23] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-11-19 19:22 ` [PATCH v21 23/23] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-11-21  6:41 ` [PATCH v21 00/23] Type2 device basic support PJ Waskiewicz
2025-11-21 10:40   ` Alejandro Lucero Palau
2025-11-22  1:08     ` PJ Waskiewicz [this message]
2025-11-28 19:44 ` PJ Waskiewicz
2025-11-28 20:29   ` Alejandro Lucero Palau
2025-11-29 16:26     ` Alejandro Lucero Palau

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