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Thu, 11 Jul 2024 01:34:55 +0000 Date: Wed, 10 Jul 2024 18:34:53 -0700 From: Dan Williams To: "Daisuke Kobayashi (Fujitsu)" , "'Dan Williams'" , "linux-cxl@vger.kernel.org" CC: "Yasunori Gotou (Fujitsu)" , "mj@ucw.cz" , "jonathan.cameron@huawei.com" Subject: RE: [PATCH v14 1/2] cxl/core/regs: Add rcd_pcie_cap initialization Message-ID: <668f36bd17043_1bc832949f@dwillia2-xfh.jf.intel.com.notmuch> References: <20240618042941.96893-1-kobayashi.da-06@fujitsu.com> <20240618042941.96893-2-kobayashi.da-06@fujitsu.com> <668df392f2036_102cc2949a@dwillia2-xfh.jf.intel.com.notmuch> <668e256583728_6de229444@dwillia2-mobl3.amr.corp.intel.com.notmuch> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: MW4PR04CA0074.namprd04.prod.outlook.com (2603:10b6:303:6b::19) To PH8PR11MB8107.namprd11.prod.outlook.com (2603:10b6:510:256::6) Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8107:EE_|DS0PR11MB7336:EE_ X-MS-Office365-Filtering-Correlation-Id: 880b9a98-8077-4d0c-13c9-08dca149ab3e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?27FjtPRTX3R7SqrxpdTO9oze2O90gmzl5d26QHEmhbQu7jC+LHfd+KkJzUos?= =?us-ascii?Q?3CRENpPOJDyHWR+eGx1j34xFQOSJenVeGNMI0En4PqYi9idPF8qj9NiQ2EbK?= =?us-ascii?Q?y9JMqfCfS7gvcqp1IlwSc+GWIq/IUG9qaerLkBvZXu5QKiqpsQiWbnshOpuh?= =?us-ascii?Q?3BVrzF2yC6YZlGzO9HnWWYzVUVq2e4aeU0j2dmaIkB+XPwotRVQuNgmroGDc?= =?us-ascii?Q?7Io587DZQcZjbBw9ueEGimMX9KYi9eOeE/I+MACQqoDFN3+sVgJ+Ct3zBmg8?= =?us-ascii?Q?ZUjpwKMp4sD4MFRAj03e8iMHHtV/hO5eMQ1m3G66WLRCgwdJgpIQu/WqfQFj?= =?us-ascii?Q?dhXbZJSdZ3fgBk3RWSdzTYUvYlK8LVJj0lnuax8IdvStdy/xe0g42QKsAYlp?= =?us-ascii?Q?AxbgwN2NVf0+UhNW0ZF4CrDSUJWvyjCY8QdzzsR7iyy4kUww+Q5gTZbu0vxw?= =?us-ascii?Q?HrW2XxtBPNpJaOQO0PiAdOOBCWGpWmaNZd4JF7+NBLQKRXIpckxGoOPvOrbw?= =?us-ascii?Q?2mvRBrWQULuVlaF3O6SF/1gwlXPxQZJp+8CKCFk+ymLLYNBq2g5Ut0gdfMFV?= =?us-ascii?Q?J/VQBLu3IWELVM2xY6SR1587mxP1Z/VpINwO6yaRpDzEIbGAHY3wai89D1RJ?= =?us-ascii?Q?nMWtf6t/eXKQY5Wnd3mDBWngsX/SaHOrlRTvsKA7JQRkiiIWAdQV0PvFD4Bw?= =?us-ascii?Q?mKFuOyHqcy4F10x+DsitZuOvuL2lkqLy7GwqfI5Dq8SWucRe3RjG2z8K+TVr?= =?us-ascii?Q?+EUyW6gOFQc2Nr9Id+7GzvWZbh3Gz3pXZjewxD+81ydCwG7WNmWWwC4hnemN?= =?us-ascii?Q?0NzyIWP2DvR4UqJgT+jRF6s9L32kT597wU7dJiXjbnX/eQvnma6P5B6Xv1I0?= =?us-ascii?Q?EYjeE+LV7KBuuZHSQLCyd1qIOJvgB+9c29/msN7Q7QfmUtI7x0zNo2QgvNIO?= =?us-ascii?Q?xsa8K4p6GaTGe+R/AgQKnRLo+tE4kwJCCENftRkSH93wAy5YTl/2xzbGLxaX?= =?us-ascii?Q?pJpFOsoGgBNqOOL0bRbcXhBblPJw0+kdhPvFaXGOWAG5Aa+PhjtSbriwzEal?= =?us-ascii?Q?XgIomZL+6ebLVFIXLnG0odTuLdkvaYxUEGSyE5UnVB7t/S39jko6Ogaer3qh?= =?us-ascii?Q?pgdAhxsTO72KZV+c7u69GGKLTJakV1df0mZLKoEa/h+9eeZhn0HoqxQsLow3?= =?us-ascii?Q?KByRFbcG3NXB7fCh6Wms6HwXkX5+d3oJeol/xYN6DZ23WlzRmp77Wf1f2fRB?= =?us-ascii?Q?pZvC3oCgGYbV39CB3XJeBUoBc6sxyIJoPkz+S48yH3prtj9yDqayderkXiNz?= =?us-ascii?Q?2tm6VeauvLnea5G7m1RPs8MNumOexW4nRFmwq14fUbtB4GlB8HQ9P78+9pbl?= =?us-ascii?Q?mHbKrQNASfV5o/aAtzSkTXjVnCwmV++Qhr9ji/7krBGpbv7QheSv6oTQJyIn?= =?us-ascii?Q?Ruonv1vncvYrzmWFrdTVjGK6PjyOHDBht7gy4J8vzwIri8HEwGAOGNScBP/U?= =?us-ascii?Q?YILhrTE5mOwGMhbfQEK1m9rGtJhcTEolhzlkbCqTotQhEC/cmolHedUQb49v?= =?us-ascii?Q?t6gL00MI/uVQGCT1b/8jfPAWzwYN8Ff4xwJa80fx9zXL0BmDItHg5FBf1UWI?= =?us-ascii?Q?vw=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 880b9a98-8077-4d0c-13c9-08dca149ab3e X-MS-Exchange-CrossTenant-AuthSource: PH8PR11MB8107.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jul 2024 01:34:55.8917 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: gbxiAoCe8RckCGzydFIuobM8meGIg+H4sOSolWOyi2ZF2Jw90Ha40zWyhtDSkrcdjHG3suwhQeHiB5TsxpGHuaOq0rG1DjaiKaynEAxIe+w= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR11MB7336 X-OriginatorOrg: intel.com Daisuke Kobayashi (Fujitsu) wrote: > Dan Williams wrote: > > Dan Williams wrote: > > > Kobayashi,Daisuke wrote: > > > > Add rcd_pcie_cap and its initialization to cache the offset of cxl1.1 > > > > device link status information. By caching it, avoid the walking > > > > memory map area to find the offset when output the register value. > > > > > > > > Reviewed-by: Jonathan Cameron > > > > Signed-off-by: "Kobayashi,Daisuke" > > > > --- > > > > drivers/cxl/core/core.h | 6 ++++ > > > > drivers/cxl/core/regs.c | 61 > > +++++++++++++++++++++++++++++++++++++++++ > > > > drivers/cxl/cxl.h | 9 ++++++ > > > > drivers/cxl/pci.c | 8 ++++-- > > > > 4 files changed, 82 insertions(+), 2 deletions(-) > > > > > > [..] > > > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > > > > index 2ff361e756d6..bbc55732d6c1 100644 > > > > --- a/drivers/cxl/pci.c > > > > +++ b/drivers/cxl/pci.c > > > > @@ -512,11 +512,15 @@ static int cxl_pci_setup_regs(struct pci_dev > > *pdev, enum cxl_regloc_type type, > > > > * is an RCH and try to extract the Component Registers from > > > > * an RCRB. > > > > */ > > > > - if (rc && type == CXL_REGLOC_RBI_COMPONENT && > > is_cxl_restricted(pdev)) > > > > + if (rc && type == CXL_REGLOC_RBI_COMPONENT && > > is_cxl_restricted(pdev)) { > > > > rc = cxl_rcrb_get_comp_regs(pdev, map); > > > > + if (rc) > > > > + return rc; > > > > > > > > - if (rc) > > > > + cxl_dport_map_rcd_linkcap(pdev); > > > > > [..] > > > Ugh, I was going to say copy what cxl_mem_probe() does around locking > > > endpoint_parent before attaching further ports, but that also appears to > > > not handle the same race. I.e. I think cxl_mem_probe() needs a fix to do > > > this as well. I will copy you on a proposed patch for that. > > > > I attempted to add the proper locking to keep cxl_dport live, but that > > runs into lockdep issues. > > > > So I think a better fix is rework dport lifetime to stay alive until the > > final put_device() of the port. In other words dport instances get added > > dynamically to the cxl_port, but only get destroyed after all port > > references are dropped. Then the @dport result from find_cxl_port() is > > not ephemeral. > > > > Given this is a latent bug that affects all current > > cxl_{mem,pci}_find_port() users, the planned fix is to just make dport > > lifetime longer, and that I will not have time to do that rework before > > v6.11 merge window, then I am ok for this lnkcap code to introduce > > another instance of the same bug. > > > > So, just make cxl_rcrb_get_comp_regs() and cxl_dport_map_rcd_linkcap() > > share the same port reference from one cxl_pci_find_port() call. > > Thanks for checking. > > I'd like to confirm my understanding of the comment. Are you suggesting that, > due to time constraints with the current patch, cxl_rcrb_get_comp_regs() and > cxl_dport_map_rcd_linkcap() should share the same dport reference as a temporary > workaround for the bug regarding the dport lifetime? What I am saying is forget the bug for now, just trust that the @dport result from cxl_pci_find_port() is valid until the put_device() on the port. > If that's what you mean, I think I can solve this problem by adding > "struct cxl_dport *dport" to the arguments of the two functions to share the reference. Yes, that's what I want for this patch, but to be clear this does not fix the bug with cxl_pci_find_port(). That bug needs deeper work that you can ignore for now. Adding another cxl_pci_find_port() user just increases the urgency to get that bug fixed. To be clear it is definitely a use after-free issue, but it needs root to be bringing ports up and down during the "cxl_pci_find_port() -> put_device(@port->dev)" window. I expect you could trigger a crash by a "modprobe -r cxl_acpi; modprobe cxl_acpi" loop while accessing these sysfs files. > In this implementation, I'm planning to run cxl_pci_find_port() in > cxl_rcrb_get_comp_regs() and share the dport obtained there. You said > that find requires a corresponding put_device(), but where is the > correct place to run it in this case? Or is it better not to run it in > this patch? So the ordering I expect is something like: port = cxl_pci_find_port(...) if (!port) return -EPROBE_DEFER; rc = cxl_rcrb_get_comp_regs(dport, ...) if (rc) goto put; rc = cxl_dport_map_rcd_linkcap(dport, ...) if (rc) goto put; put: put_device(...) return rc;