Re: [PATCH 1/1] cxl/pci: Check dport->regs.rcd_pcie_cap availability before accessing

[Dan Williams <dan.j.williams@intel.com>]

Li Ming wrote:
> RCD Upstream Port's PCI Express Capability is a component registers
> block stored in RCD Upstream Port RCRB. CXL PCI driver helps to map it
> during the RCD probing, but mapping failure is allowed for component
> registers blocks in CXL PCI driver.
> 
> dport->regs.rcd_pcie_cap is used to store the virtual address of the RCD
> Upstream Port's PCI Express Capability, add a dport->regs.rcd_pcie_cap
> checking in rcd_pcie_cap_emit() just in case user accesses a invalid
> address via RCD sysfs.
> 
> Fixes: c5eaec79fa43 ("cxl/pci: Add sysfs attribute for CXL 1.1 device link status")
> Signed-off-by: Li Ming <ming.li@zohomail.com>

Hi Ming,

This patch looks ok.

Reviewed-by: Dan Williams <dan.j.williams@intel.com>

...but it bothers me that the sysfs attributes are visible while the
attributes are in this -ENXIO return state. I will throw together a
follow-on patch to hide the attributes altogether when these
preconditions are not met.