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From: Ira Weiny <ira.weiny@intel.com>
To: <shiju.jose@huawei.com>, <dave.jiang@intel.com>,
	<dan.j.williams@intel.com>, <jonathan.cameron@huawei.com>,
	<alison.schofield@intel.com>, <nifan.cxl@gmail.com>,
	<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
	<dave@stgolabs.net>, <linux-cxl@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <linuxarm@huawei.com>,
	<tanxiaofei@huawei.com>, <prime.zeng@hisilicon.com>,
	<shiju.jose@huawei.com>
Subject: Re: [PATCH v6 4/6] cxl/events: Update DRAM Event Record to CXL spec rev 3.1
Date: Mon, 13 Jan 2025 10:22:04 -0600	[thread overview]
Message-ID: <67853dacb9a2_1817af294c3@iweiny-mobl.notmuch> (raw)
In-Reply-To: <20250111091756.1682-5-shiju.jose@huawei.com>

shiju.jose@ wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
> 
> CXL spec 3.1 section 8.2.9.2.1.2 Table 8-46, DRAM Event Record has updated
> with following new fields and new types for Memory Event Type, Transaction
> Type and Validity Flags fields.
> 1. Component Identifier
> 2. Sub-channel
> 3. Advanced Programmable Corrected Memory Error Threshold Event Flags
> 4. Corrected Memory Error Count at Event
> 5. Memory Event Sub-Type
> 
> Update DRAM events record and DRAM trace event for the above spec
> changes. The new fields are inserted in logical places.
> Includes trivial consistency of white space improvements.
> 
> Example trace print of cxl_dram trace event,
> 
> cxl_dram: memdev=mem0 host=0000:0f:00.0 serial=3 log=Informational : \
> time=54799339519 uuid=601dcbb3-9c06-4eab-b8af-4e9bfb5c9624 len=128 \
> flags='0x1' handle=1 related_handle=0 maint_op_class=1 \
> maint_op_sub_class=3 : dpa=18680 dpa_flags='' \
> descriptor='UNCORRECTABLE_EVENT|THRESHOLD_EVENT' type='Data Path Error' \
> sub_type='Media Link CRC Error' transaction_type='Internal Media Scrub' \
> channel=3 rank=17 nibble_mask=3b00b2 bank_group=7 bank=11 row=2 \
> column=77 cor_mask=21 00 00 00 00 00 00 00 2c 00 00 00 00 00 00 00 37 00 \
> 00 00 00 00 00 00 42 00 00 00 00 00 00 00 validity_flags='CHANNEL|RANK|NIBBLE|\
> BANK GROUP|BANK|ROW|COLUMN|CORRECTION MASK|COMPONENT|COMPONENT PLDM FORMAT' \
> comp_id=01 74 c5 08 9a 1a 0b fc d2 7e 2f 31 9b 3c 81 4d \
> comp_id_pldm_valid_flags='PLDM Entity ID' pldm_entity_id=74 c5 08 9a 1a 0b \
> pldm_resource_id=0x00 hpa=ffffffffffffffff region= \
> region_uuid=00000000-0000-0000-0000-000000000000 sub_channel=5 \
> cme_threshold_ev_flags='Corrected Memory Errors in Multiple Media Components|\
> Exceeded Programmable Threshold' cvme_count=148
> 
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>

Reviewed-by: Ira Weiny <ira.weiny@intel.com>

  reply	other threads:[~2025-01-13 16:22 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-11  9:17 [PATCH v6 0/6] Update Event Records to CXL spec rev 3.1 shiju.jose
2025-01-11  9:17 ` [PATCH v6 1/6] cxl/events: Update Common Event Record " shiju.jose
2025-01-11  9:17 ` [PATCH v6 2/6] cxl/events: Add Component Identifier formatting for " shiju.jose
2025-01-11  9:17 ` [PATCH v6 3/6] cxl/events: Update General Media Event Record to " shiju.jose
2025-01-11  9:17 ` [PATCH v6 4/6] cxl/events: Update DRAM " shiju.jose
2025-01-13 16:22   ` Ira Weiny [this message]
2025-01-11  9:17 ` [PATCH v6 5/6] cxl/events: Update Memory Module " shiju.jose
2025-01-11  9:17 ` [PATCH v6 6/6] cxl/test: Update test code for event records " shiju.jose
2025-01-13 16:55 ` [PATCH v6 0/6] Update Event Records " Dave Jiang

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