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Thu, 23 Jan 2025 20:24:26 +0000 Date: Thu, 23 Jan 2025 12:24:24 -0800 From: Dan Williams To: Jonathan Cameron , Dan Williams CC: , Dave Jiang , "Alejandro Lucero" , Ira Weiny Subject: Re: [PATCH v2 3/5] cxl: Introduce 'struct cxl_dpa_partition' and 'struct cxl_range_info' Message-ID: <6792a578374f4_20fa294b3@dwillia2-xfh.jf.intel.com.notmuch> References: <173753635014.3849855.17902348420186052714.stgit@dwillia2-xfh.jf.intel.com> <173753636727.3849855.464861650807086965.stgit@dwillia2-xfh.jf.intel.com> <20250123160915.00002012@huawei.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250123160915.00002012@huawei.com> X-ClientProxiedBy: MW4PR04CA0153.namprd04.prod.outlook.com (2603:10b6:303:85::8) To PH8PR11MB8107.namprd11.prod.outlook.com (2603:10b6:510:256::6) Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8107:EE_|DS0PR11MB7788:EE_ X-MS-Office365-Filtering-Correlation-Id: 9bcab80d-2324-4a05-c5eb-08dd3bebeeb6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|366016; 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Trip hazards include: > > > > - CXL Memory Devices need to consider a PMEM partition, but Accelerator > > devices with CXL.mem likely do not in the common case. > > > > - CXL Memory Devices enumerate DPA through Memory Device mailbox > > commands like Partition Info, Accelerators devices do not. > > > > - CXL Memory Devices that support DCD support more than 2 partitions. > > Some of the driver algorithms are awkward to expand to > 2 partition > > cases. > > > > - DPA performance data is a general capability that can be shared with > > accelerators, so tracking it in 'struct cxl_memdev_state' is no longer > > suitable. > > > > - Hardcoded assumptions around the PMEM partition always being index-1 > > if RAM is zero-sized or PMEM is zero sized. > > > > - 'enum cxl_decoder_mode' is sometimes a partition id and sometimes a > > memory property, it should be phased in favor of a partition id and > > the memory property comes from the partition info. > > > > Towards cleaning up those issues and allowing a smoother landing for the > > aforementioned pending efforts, introduce a 'struct cxl_dpa_partition' > > array to 'struct cxl_dev_state', and 'struct cxl_range_info' as a shared > > way for Memory Devices and Accelerators to initialize the DPA information > > in 'struct cxl_dev_state'. > > > > For now, split a new cxl_dpa_setup() from cxl_mem_create_range_info() to > > get the new data structure initialized, and cleanup some qos_class init. > > Follow on patches will go further to use the new data structure to > > cleanup algorithms that are better suited to loop over all possible > > partitions. > > > > cxl_dpa_setup() follows the locking expectations of mutating the device > > DPA map, and is suitable for Accelerator drivers to use. Accelerators > > likely only have one hardcoded 'ram' partition to convey to the > > cxl_core. > > > > Link: http://lore.kernel.org/20241230214445.27602-1-alejandro.lucero-palau@amd.com [1] > > Link: http://lore.kernel.org/20241210-dcd-type2-upstream-v8-0-812852504400@intel.com [2] > > Cc: Dave Jiang > > Cc: Alejandro Lucero > > Cc: Ira Weiny > > Signed-off-by: Dan Williams > > > A few trivial comments inline but looking better to me. > > One question about what smells to me like our next MIXED mode. > > [..] > > diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c > > index b177a488e29b..5400a421ad30 100644 > > --- a/drivers/cxl/core/cdat.c > > +++ b/drivers/cxl/core/cdat.c > > > +/* if this fails the caller must destroy @cxlds, there is no recovery */ > > +int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info) > > +{ > > + struct device *dev = cxlds->dev; > > + > > + guard(rwsem_write)(&cxl_dpa_rwsem); > > + > > + if (cxlds->nr_partitions) > > + return -EBUSY; > > + > > + if (!info->size || !info->nr_partitions) { > > + cxlds->dpa_res = DEFINE_RES_MEM(0, 0); > > + cxlds->nr_partitions = 0; > > + return 0; > > + } > > + > > + cxlds->dpa_res = DEFINE_RES_MEM(0, info->size); > > + > > + for (int i = 0; i < info->nr_partitions; i++) { > > + const struct cxl_dpa_part_info *part = &info->part[i]; > > + const char *desc; > > + int rc; > > + > > + if (part->mode == CXL_PARTMODE_RAM) > > + desc = "ram"; > > + else if (part->mode == CXL_PARTMODE_PMEM) > > + desc = "pmem"; > > I'd go switch statement now to save having to fix this up later, or > an array of strings with a bounds check. > (not important though if you want to shunt that into another day) Might as well do it now. [..] > > diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h > > index 78e92e24d7b5..15f549afab7c 100644 > > --- a/drivers/cxl/cxlmem.h > > +++ b/drivers/cxl/cxlmem.h > > @@ -97,6 +97,25 @@ int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, > > resource_size_t base, resource_size_t len, > > resource_size_t skipped); > > > > +enum cxl_partition_mode { > > + CXL_PARTMODE_NONE, > > What is NONE for? Given you are now packing the partitions and > counting them when would we get an 'empty' one? Looks like another thinko during the conversion. It gets used later on in the series to check for endpoint-decoders that have not been assigned a partition. However, that path also guarantees that the endpoint decoder *has* been assigned. So long CXL_PARTMODE_NONE, we hardly knew ye.