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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?PQvpfEntnAO173tDzI0meyQxMM6LZCJcX0zeD/0r/GlCV5a8YFPVFVE5gEKN?= =?us-ascii?Q?2I83Y5VXLY1wYy5KX8oqC+6xrLxs4a75Ud9heSaLX36q2sR/IVf9gqKxn6Os?= =?us-ascii?Q?B2H9qyXoUWOQNFMN58J8X5TTGExRAKC+V4S+bHJIaKPw25IHbd0Zuy8SBrC+?= =?us-ascii?Q?ZEpveAFEW74NfVJ5sfLTfeakaRwCTM0ltg2uqJRNroi8jJViWPX1vMeTFSpa?= =?us-ascii?Q?My9A5Dhvp8hDuXyMErD47ihr5YXlRJCJuRGhBhRPIZnJZDZdZZmNtVI6vI/e?= =?us-ascii?Q?D4eciXBcg3SRaW6C4vZc+ApYQr5vpHWlmhPh+7RU8e11K+BcRg5f56xG7G5a?= =?us-ascii?Q?L0jDlNLCInEQZTFPy1BJSamamLMwT9ENMedeKseNCyaHW051rwlc8E1v+msM?= =?us-ascii?Q?g/wtFbouQ8d8ZkZHlpQmm8XNCkUPFg4YArTPfjb5P3ijpU48g82ZanGCniIW?= =?us-ascii?Q?HwsvMFL3zrInGbHoYaiABONtSm/3WWgmOIwIwiA/ozosqUF+QoDBpMwo6Xcf?= =?us-ascii?Q?C1ubZB8sn12vHBpu/dpI4dK+mF5dpeGVQ8RieA7T9anDtszY3AfRCmA8ltbc?= =?us-ascii?Q?uDXFZB85ooo3EsRsHpWldw3VEw8uiYMXBr4Muji3eV5y/Nsy5dyxCqkgcekz?= =?us-ascii?Q?TtF60ITOyS2/pARjgOiDD2CWYHbmK84LaJedca2qyVDGYbBZVvnDCh/Hvs8C?= =?us-ascii?Q?nZPBY+zjd8Y4d449c8TIhX2Nsxcuda4xqs4nuxnKrC3YDGX8+vgWNo1crwSY?= =?us-ascii?Q?bkTAyxg8HsuzLDLbtz9vYiVKUkdVeYM+SI6weFb0g1R/SJZaqg3nA1dl9gKF?= =?us-ascii?Q?YUEe9RpN+bDPpdK6SY//Di1H+MVm7NuVGJ3raf6N89vhmDYZgoyoCcH0J7Rx?= =?us-ascii?Q?1T/MjazjX/nFCOjDNzGyNnpH1Te+yy7tEL9zJV1JEEX5zrpGyHbRnDdO3V9D?= =?us-ascii?Q?IMMapxdQOqo5oZvqyZ5hdHHZpU+DAymwfwuvMfRpR2jnyDhb3tiK23vVwHd1?= =?us-ascii?Q?yfolgurRTNvevqgnSdaiLqfoQXiHqxGG8yED6CwAxBvq+mjzRfTMXNNowvGk?= =?us-ascii?Q?Vd5wGUcb34qQVevIfz1EkRE9od38YWU2L4pcpK6o3d3cTIh9TR1nivIbEoCJ?= =?us-ascii?Q?rcnLMs3qr57DQEGFpp2QvK7wyOhAaY3W1nnXvh3dXUx3hi2mXhbfbpfOT6Xi?= =?us-ascii?Q?a4cuhvktZSuaoK/a82+RzcUEVZAkbHzGzB9PvvTd6x9ZQhYHJZGkjrM/K72i?= =?us-ascii?Q?a0QBzb/OrLOn0VFGMAxtdwCpX6n/RISe1kfP5+MM83Li5kcciZHMaXCn6zkH?= =?us-ascii?Q?xppgv2uQOHdSZSksH1oPv6DtUJvzGWhV0nxauy0dD0yq+5xdHohP1/+uVgiS?= =?us-ascii?Q?57JgLY1ffTMJBijTVSy9E9Y2tHZPNfFTjXcL9KCXWe/2YTamhrx+npEgfAEs?= =?us-ascii?Q?PY/HjShqF6lLoo/jIywkiAgTEQzlZTEnWJ6ZZ2FxcFWItOwvD7OvRIyBN9mO?= =?us-ascii?Q?SpZGPjVnHdrk+PdWA2TJzCta/SsIc+Lg9ZuxDUruaD3WO2+hdIUE97uu7kAQ?= =?us-ascii?Q?RC2csP0GNNtHWY4VxUlIeXuNrxE46BMFCfv16SJ9?= X-MS-Exchange-CrossTenant-Network-Message-Id: 3c07fb96-4434-46fc-c0d9-08dd479b1a37 X-MS-Exchange-CrossTenant-AuthSource: SA1PR11MB6733.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Feb 2025 17:16:04.4247 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 291tfPV/SDGgoojmXJKFqgYugendm8PM6VL522qTlWS8Or46HEI5KIiqcIh84wRzLnd/+lKQ/lDFYdr/vevs7Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR11MB8578 X-OriginatorOrg: intel.com Srirangan Madhavan wrote: Generally this looks good. Some minor issues below. > This change adds the support and implements the CXL reset > steps as laid out by the CXL Spec v3.1 Sections 9.6 & 9.7. > > With support for Type 2 devices being introduced, more devices will > require finer-grained reset mechanisms beyond bus-wide reset methods. > > This change defines the necessary CXL DVSEC register macros. > For devices that support CXL Reset, cache lines are disabled, WB+I is > asserted, wait for cache invalid status, Mem Clr bit is asserted and > finally reset is initiated. This commit message should be in the imperative. For example: "Type 2 devices are being introduced and will require finer-grained reset. Add support for CXL reset per CXL v3.1 Section 9.6/9.7." The rest of the details are given in the code itself. BTW why not just update to 3.2? > > Signed-off-by: Srirangan Madhavan > --- > drivers/pci/pci.c | 183 ++++++++++++++++++++++++++++++++++ > include/linux/pci.h | 2 +- > include/uapi/linux/pci_regs.h | 25 +++++ > 3 files changed, 209 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index 869d204a70a3..cf6009f5bd6c 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -5026,6 +5026,12 @@ static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe) > return pci_reset_hotplug_slot(dev->slot->hotplug, probe); > } > > +static u16 cxl_device_dvsec(struct pci_dev *dev) > +{ > + return pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, > + PCI_DVSEC_CXL_DEV); > +} NIT: probably not worth having a whole function but... > + > static u16 cxl_port_dvsec(struct pci_dev *dev) > { > return pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, > @@ -5116,6 +5122,182 @@ static int cxl_reset_bus_function(struct pci_dev *dev, bool probe) > return rc; > } > > +static int cxl_reset_prepare(struct pci_dev *dev, u16 dvsec) > +{ > + u16 reg, val, cap; > + int rc; > + u32 timeout_us = 100, timeout_tot_us = 10000; > + > + /* > + * Wait for any pending transactions. > + * Assuming this does cxl.io stuff. > + */ The comment here is generally not needed. In particular the first sentence is the same as the function name being called. > + if (!pci_wait_for_pending_transaction(dev)) > + pci_err(dev, "timed out waiting for pending transaction; performing cxl reset anyway\n"); > + > + /* > + * Disable caching and then write back and invalidate lines. > + */ I think this comment is wrong... > + rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCAP, > + &cap); > + if (rc) > + return rc; > + > + if (!(cap & PCI_DVSEC_CXL_DEVCAP_CACHE_CAPABLE)) > + return 0; Isn't this checking for a cache capable device? > + > + /* > + * Disable cache. > + * WB and invalidate cahce if capability is advertised. > + */ Then disabling and invalidating the cache here. > + rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2, > + ®); > + if (rc) > + return rc; > + val = reg | PCI_DVSEC_CXL_DEVCTL2_DISABLE_CACHING; > + > + if (cap & PCI_DVSEC_CXL_DEVCAP_CACHE_WB_INVALIDATE) > + val = reg | PCI_DVSEC_CXL_DEVCTL2_INIT_CACHE_WB_INVALIDATE; > + pci_write_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2, > + val); > + > + /* > + * From Section 9.6: "Software may leverage the cache size reported in > + * the DVSEC CXL Capability2 register to compute a suitable timeout > + * value". > + * Given there is no conversion factor for cache size -> timeout, > + * setting timer for default 10ms. > + */ > + do { > + if (timeout_tot_us < 0) > + return -ETIMEDOUT; > + usleep_range(timeout_us, timeout_us+1); > + timeout_tot_us -= timeout_us; > + rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2, > + ®); > + if (rc) > + return rc; > + } while (!(reg & PCI_DVSEC_CXL_DEVSTATUS2_CACHE_INVALID)); > + > + return 0; > +} > + > +/** > + * cxl_reset_init - initiate a cxl reset > + * @dev: device to reset @dvsec? > + * > + * Initiate a cxl reset. > + */ Given this is a static internal call it seems best to leave out the kdoc altogether rather than add the dvsec parameter to the doc. > +static int cxl_reset_init(struct pci_dev *dev, u16 dvsec) > +{ > + u16 reg, val; > + u32 timeout_ms; > + int rc; > + u32 reset_timeouts_ms[] = {10, 100, 1000, 10000, 100000}; NIT: Maybe... give the spec reference for the timeout values. > + > + /* > + * Check if CXL Reset MEM CLR is supported. > + */ > + rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCAP, > + ®); > + if (rc) > + return rc; > + > + if (reg & PCI_DVSEC_CXL_DEVCAP_CXL_RST_MEM_CLR) { > + rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2, > + ®); > + if (rc) > + return rc; > + > + val = reg | PCI_DVSEC_CXL_DEVCTL2_CXL_RST_MEM_CLR_ENABLE; > + pci_write_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2, > + val); > + } > + > + /* > + * Read timeout value > + */ > + rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCAP, > + ®); > + if (rc) > + return rc; > + timeout_ms = reset_timeouts_ms[FIELD_GET(PCI_DVSEC_CXL_DEVCAP_CXL_RST_TIMEOUT_MASK, reg)]; > + > + /* > + * Write reset config > + */ > + rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2, > + ®); > + if (rc) > + return rc; > + > + val = reg | PCI_DVSEC_CXL_DEVCTL2_CXL_INIT_RST; > + pci_write_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2, > + val); > + > + /* > + * Wait till timeout and then check reset status is complete. > + */ > + msleep(timeout_ms); > + rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVSTATUS2, > + ®); > + if (rc) > + return rc; > + if (reg & PCI_DVSEC_CXL_DEVSTATUS2_RST_ERR || > + ~reg & PCI_DVSEC_CXL_DEVSTATUS2_RST_COMPLETE) > + return -ETIMEDOUT; > + > + /* > + * Revert cashing disable. NIT caching Probably best to remove the comment. > + */ > + rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2, > + ®); > + if (rc) > + return rc; > + val = (reg & (~PCI_DVSEC_CXL_DEVCTL2_DISABLE_CACHING)); > + pci_write_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCTL2, > + val); > + > + return 0; > +} > + > +/** > + * cxl_reset - initiate a cxl reset > + * @dev: device to reset > + * @probe: if true, return 0 if device can be reset this way > + * > + * Initiate a cxl reset on @dev. > + */ > +static int cxl_reset(struct pci_dev *dev, bool probe) > +{ > + u16 dvsec, reg; > + int rc; > + > + dvsec = cxl_device_dvsec(dev); > + if (!dvsec) > + return -ENOTTY; > + > + /* > + * Check if CXL Reset is supported. > + */ > + rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_DEVCAP, > + ®); > + if (rc) > + return -ENOTTY; > + > + if (~(reg & PCI_DVSEC_CXL_DEVCAP_CXL_RST)) > + return -ENOTTY; > + > + if (probe) > + return 0; > + > + rc = cxl_reset_prepare(dev, dvsec); > + if (rc) > + return rc; > + > + return cxl_reset_init(dev, dvsec); > +} > + > void pci_dev_lock(struct pci_dev *dev) > { > /* block PM suspend, driver probe, etc. */ > @@ -5202,6 +5384,7 @@ const struct pci_reset_fn_method pci_reset_fn_methods[] = { > { pci_dev_acpi_reset, .name = "acpi" }, > { pcie_reset_flr, .name = "flr" }, > { pci_af_flr, .name = "af_flr" }, > + { cxl_reset, .name = "cxl_reset" }, > { pci_pm_reset, .name = "pm" }, > { pci_reset_bus_function, .name = "bus" }, > { cxl_reset_bus_function, .name = "cxl_bus" }, > diff --git a/include/linux/pci.h b/include/linux/pci.h > index 47b31ad724fa..efcb06598f26 100644 > --- a/include/linux/pci.h > +++ b/include/linux/pci.h > @@ -51,7 +51,7 @@ > PCI_STATUS_PARITY) > > /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ > -#define PCI_NUM_RESET_METHODS 8 > +#define PCI_NUM_RESET_METHODS 9 > > #define PCI_RESET_PROBE true > #define PCI_RESET_DO_RESET false > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index 3445c4970e4d..52618c5b095d 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -1209,6 +1209,31 @@ > #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX 0xff000000 > > /* Compute Express Link (CXL r3.1, sec 8.1.5) */ v3.2 Ira [snip]