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From: Dan Williams <dan.j.williams@intel.com>
To: Yiannis Nikolakopoulos <yi.nikolakop@gmail.com>,
	Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <yiannis@zptcorp.com>
Subject: Re: dax behavior on CXL 1.1 hosts
Date: Wed, 21 May 2025 14:57:12 -0700	[thread overview]
Message-ID: <682e4c386cbf3_1626e1007b@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <CA+CExOjX2f5BOVu4bAGDRS11EwLevefJ7ziPHHUSK-hCFsZkPQ@mail.gmail.com>

Yiannis Nikolakopoulos wrote:
> On Tue, 20 May 2025 at 00:56, Dan Williams <dan.j.williams@intel.com> wrote:
[..]
> > Until then, the workaround is to disable the cxl_acpi driver from
> > loading. When cxl_acpi is disabled, dax_hmem proceeds to produce a raw
> > dax device. That configuration forfeits all the RAS support, but that is
> > to be expected when the CXL subsystem needs help to parse the system
> > topology.
> Indeed the workaround works as expected, thank you very much for that.
> 
> Nevertheless, if figuring out the quirks of this platform provides any value to
> the core driver and the community here, I can find some time within the next
> couple of weeks to debug and delve deeper. I can of course give more details
> on the platform, logs etc.

One of the larger known platform quirks that gives the CXL subsystem
heartburn are platforms that translate CXL HPA to another address space.
Patches in-flight to address that are here:

http://lore.kernel.org/20250218132356.1809075-1-rrichter@amd.com

      reply	other threads:[~2025-05-21 21:57 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-15 22:50 dax behavior on CXL 1.1 hosts Yiannis Nikolakopoulos
2025-05-19 22:56 ` Dan Williams
2025-05-21 21:22   ` Yiannis Nikolakopoulos
2025-05-21 21:57     ` Dan Williams [this message]

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