Re: [PATCH v10 02/17] PCI/CXL: Add pcie_is_cxl()

[<dan.j.williams@intel.com>]

Bowman, Terry wrote:
> 
> 
> On 7/23/2025 5:30 PM, dan.j.williams@intel.com wrote:
> > Terry Bowman wrote:
> >> CXL and AER drivers need the ability to identify CXL devices.
> >>
> >> Add set_pcie_cxl() with logic checking for CXL Flexbus DVSEC presence. The
> >> CXL Flexbus DVSEC presence is used because it is required for all the CXL
> >> PCIe devices.[1]
> >>
> >> Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL
> >> Flexbus presence.
> >>
> >> Add function pcie_is_cxl() to return 'struct pci_dev::is_cxl'.
> >>
> >> [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended
> >>     Capability (DVSEC) ID Assignment, Table 8-2
> >>
[..]
> >> +static void set_pcie_cxl(struct pci_dev *dev)
> >> +{
> >> +	u16 dvsec = pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL,
> >> +					      PCI_DVSEC_CXL_FLEXBUS);
> >> +	if (dvsec)
> >> +		dev->is_cxl = 1;
> >> +}
> >> +
> >>  static void set_pcie_untrusted(struct pci_dev *dev)
> >>  {
> >>  	struct pci_dev *parent = pci_upstream_bridge(dev);
> >> @@ -2021,6 +2029,8 @@ int pci_setup_device(struct pci_dev *dev)
> >>  	/* Need to have dev->cfg_size ready */
> >>  	set_pcie_thunderbolt(dev);
> >>  
> >> +	set_pcie_cxl(dev);
> > Per the comment in the header below, in the case of upstream ports and
> > endpoints, this should walk to the parent downstream port and make sure
> > the cxl setting matches. I.e. with hotplug the downstream port may
> > transition from not-cxl to is-cxl. Update downstream-port parents at the
> > beginning of life of their CXL child-devices.
> Ok.
> 
> The check you describe for EPs and UPs would be in is_cxl(), right?

Hmm, no I was considering something like this:

static void set_pcie_cxl(struct pci_dev *dev)
{
        struct pci_dev *parent;
        u16 dvsec = pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL,
                                              PCI_DVSEC_CXL_FLEXBUS);
        if (dvsec)
                dev->is_cxl = 1;
        
        if (!pci_is_pcie(dev) ||
            !(pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT ||
              pci_pcie_type(dev) == PCI_EXP_TYPE_UPSTREAM))
                return;

        parent = pci_upstream_bridge(dev);
        set_pcie_cxl(parent);
}

I.e. whenever a new device is scanned there is a chance its upstream
bridge's CXL link has changed state. There is still a chance that the
kernel sees them out of sync for a moment if the link is bouncing, but
for the happy case I think this closes some of the mismatch gap.