From: <dan.j.williams@intel.com>
To: "Bowman, Terry" <terry.bowman@amd.com>,
<dan.j.williams@intel.com>, <dave@stgolabs.net>,
<jonathan.cameron@huawei.com>, <dave.jiang@intel.com>,
<alison.schofield@intel.com>, <bhelgaas@google.com>,
<shiju.jose@huawei.com>, <ming.li@zohomail.com>,
<Smita.KoralahalliChannabasappa@amd.com>, <rrichter@amd.com>,
<dan.carpenter@linaro.org>, <PradeepVineshReddy.Kodamati@amd.com>,
<lukas@wunner.de>, <Benjamin.Cheatham@amd.com>,
<sathyanarayanan.kuppuswamy@linux.intel.com>,
<linux-cxl@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>
Subject: Re: [PATCH v10 04/17] CXL/AER: Introduce CXL specific AER driver file
Date: Thu, 24 Jul 2025 13:23:41 -0700 [thread overview]
Message-ID: <6882964d627d8_134cc710044@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <536c6bde-fe1c-400b-a8bc-bb40a23ef9fa@amd.com>
Bowman, Terry wrote:
> On 7/23/2025 8:16 PM, dan.j.williams@intel.com wrote:
> > Terry Bowman wrote:
> >> The CXL AER error handling logic currently resides in the AER driver file,
> >> drivers/pci/pcie/aer.c. CXL specific changes are conditionally compiled
> >> using #ifdefs.
> >>
> >> Improve the AER driver maintainability by separating the CXL specific logic
> >> from the AER driver's core functionality and removing the #ifdefs.
> >> Introduce drivers/pci/pcie/cxl_aer.c and move the CXL AER logic into the
> >> new file.
> >>
> >> Update the makefile to conditionally compile the CXL file using the
> >> existing CONFIG_PCIEAER_CXL Kconfig.
> >>
> >> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> >> ---
> > After reading patch5 I want to qualify my Reviewed-by:...
> >
> >> drivers/pci/pci.h | 8 +++
> >> drivers/pci/pcie/Makefile | 1 +
> >> drivers/pci/pcie/aer.c | 138 -------------------------------------
> >> drivers/pci/pcie/cxl_aer.c | 138 +++++++++++++++++++++++++++++++++++++
> > This is a poor name for this file because the functionality only relates to
> > code that supports a dead-end generation of RCH / RCD hardware platforms.
> >
> > I do agree that it should be removed from aer.c so typical PCIe AER
> > maintenance does not need to trip over that cruft.
> >
> > Please call it something like rch_aer.c so it is tucked out of the way,
> > sticks out as odd in any future diffstat, and does not confuse from the
> > CXL VH error handling that supports current and future generation
> > hardware.
> >
> > Perhaps even move it to its own silent Kconfig symbol with a deprecation
> > warning, something like below, so someone remembers to delete it.
>
> cxl_rch_handle_error_iter() and cxl_rch_handle_error() need to be moved from pci/pcie/cxl_aer.c
> into cxl/core/native_ras.c introduced in this series. There is no RCH or VH handling in cxl_aer.c.
> cxl_aer.c serves to detect if an error is a CXL error and if it is then it forwards it to the
> CXL drivers using the kfifo introduced later. I will update the commit message stating more
> will be added later.
Wait, this set moves the same function to a new file twice in the same
set? I had not gotten that far along, but that's not acceptable.
The reasons I had assumed that the rch bits would remain as a vestigial
drivers/pci/pcie/rch_aer.c file to be cut from the kernel later are:
- The goal of forwarding protocol errors to the cxl_core is that the
cxl_core maintains a cxl_port hierarchy. For the RCH case there is no
hierarchy and little to no value in being able disposition or decorate
error reports with the cxl_port driver.
- The RCH code requires a series of new PCI core exports for this
one-off unfortunate mistake of history where the CXL specification
tried way too hard to hide the presence of CXL. If this code is
already on a deprecation path, that contraindicates new exports.
> Dave Jiang introduced cxl/core/pci_aer.c I understand the name is still up for possible change.
> The native_ras.c changes in this series is planned to be moved into cxl/core/pci_aer.c for v11.
> The files were created with the same purpose but we used different filenames and need to converge.
Why not put this stuff in the existing cxl/core/ras.c? I do expect that
we want to route CPER reports to cxl_port objects at some point, so the
"native" distinction is more confusing than beneficial as far as I can
see.
next prev parent reply other threads:[~2025-07-24 20:23 UTC|newest]
Thread overview: 87+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-26 22:42 [PATCH v10 00/17] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2025-06-26 22:42 ` [PATCH v10 01/17] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Terry Bowman
2025-07-18 17:55 ` Dave Jiang
2025-07-23 21:58 ` dan.j.williams
2025-07-23 22:15 ` Dave Jiang
2025-06-26 22:42 ` [PATCH v10 02/17] PCI/CXL: Add pcie_is_cxl() Terry Bowman
2025-07-23 22:30 ` dan.j.williams
2025-07-23 23:21 ` Bowman, Terry
2025-07-24 18:00 ` dan.j.williams
2025-08-09 10:56 ` Alejandro Lucero Palau
2025-08-11 19:14 ` Bowman, Terry
2025-08-11 23:14 ` dan.j.williams
2025-06-26 22:42 ` [PATCH v10 03/17] PCI/AER: Report CXL or PCIe bus error type in trace logging Terry Bowman
2025-06-26 23:25 ` Sathyanarayanan Kuppuswamy
2025-06-27 14:14 ` Bowman, Terry
2025-06-27 9:53 ` Jonathan Cameron
2025-07-02 16:00 ` Bowman, Terry
2025-06-27 11:32 ` Shiju Jose
2025-06-27 14:24 ` Bowman, Terry
2025-07-01 21:27 ` Dave Jiang
2025-07-23 22:56 ` dan.j.williams
2025-06-26 22:42 ` [PATCH v10 04/17] CXL/AER: Introduce CXL specific AER driver file Terry Bowman
2025-06-26 23:42 ` Sathyanarayanan Kuppuswamy
2025-06-27 10:12 ` Jonathan Cameron
2025-06-27 14:29 ` Bowman, Terry
2025-07-24 0:01 ` dan.j.williams
2025-07-24 17:06 ` Bowman, Terry
2025-07-24 20:32 ` dan.j.williams
2025-07-24 1:16 ` dan.j.williams
2025-07-24 17:02 ` Bowman, Terry
2025-07-24 20:23 ` dan.j.williams [this message]
2025-06-26 22:42 ` [PATCH v10 05/17] CXL/AER: Introduce kfifo for forwarding CXL errors Terry Bowman
2025-06-27 10:24 ` Jonathan Cameron
2025-07-02 16:21 ` Bowman, Terry
2025-07-02 19:54 ` Dan Carpenter
2025-07-02 19:57 ` Bowman, Terry
2025-07-03 10:06 ` Jonathan Cameron
2025-07-01 21:53 ` Dave Jiang
2025-07-02 17:10 ` Bowman, Terry
2025-07-24 2:01 ` dan.j.williams
2025-07-24 17:21 ` Bowman, Terry
2025-07-24 20:55 ` dan.j.williams
2025-06-26 22:42 ` [PATCH v10 06/17] PCI/AER: Dequeue forwarded CXL error Terry Bowman
2025-06-27 11:00 ` Jonathan Cameron
2025-07-02 17:51 ` Bowman, Terry
2025-07-01 23:04 ` Dave Jiang
2025-07-02 17:56 ` Bowman, Terry
2025-07-03 10:11 ` Jonathan Cameron
2025-07-25 0:38 ` dan.j.williams
2025-06-26 22:42 ` [PATCH v10 07/17] CXL/PCI: Introduce CXL uncorrectable protocol error recovery Terry Bowman
2025-06-27 11:05 ` Jonathan Cameron
2025-07-02 21:06 ` Bowman, Terry
2025-06-27 12:27 ` Shiju Jose
2025-07-02 21:34 ` Bowman, Terry
2025-06-26 22:42 ` [PATCH v10 08/17] cxl/pci: Move RAS initialization to cxl_port driver Terry Bowman
2025-06-27 11:12 ` Jonathan Cameron
2025-07-18 18:01 ` Dave Jiang
2025-06-26 22:42 ` [PATCH v10 09/17] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2025-06-27 11:17 ` Jonathan Cameron
2025-07-02 21:41 ` Bowman, Terry
2025-07-18 21:28 ` Dave Jiang
2025-07-18 21:55 ` Bowman, Terry
2025-07-18 22:01 ` Dave Jiang
2025-07-18 22:40 ` Bowman, Terry
2025-07-18 22:45 ` Dave Jiang
2025-06-26 22:42 ` [PATCH v10 10/17] cxl/pci: Update RAS handler interfaces to also support CXL Ports Terry Bowman
2025-06-26 22:42 ` [PATCH v10 11/17] cxl/pci: Log message if RAS registers are unmapped Terry Bowman
2025-07-21 21:56 ` Dave Jiang
2025-06-26 22:42 ` [PATCH v10 12/17] cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports Terry Bowman
2025-06-27 12:22 ` Shiju Jose
2025-07-02 1:18 ` Alison Schofield
2025-07-02 22:07 ` Bowman, Terry
2025-07-02 21:56 ` Bowman, Terry
2025-06-26 22:42 ` [PATCH v10 13/17] cxl/pci: Update cxl_handle_cor_ras() to return early if no RAS errors Terry Bowman
2025-06-27 11:48 ` Jonathan Cameron
2025-07-21 22:17 ` Dave Jiang
2025-06-26 22:42 ` [PATCH v10 14/17] cxl/pci: Introduce CXL Endpoint protocol error handlers Terry Bowman
2025-06-27 11:52 ` Jonathan Cameron
2025-06-27 12:27 ` Shiju Jose
2025-07-21 22:35 ` Dave Jiang
2025-07-22 18:23 ` Bowman, Terry
2025-06-26 22:42 ` [PATCH v10 15/17] CXL/PCI: Introduce CXL Port " Terry Bowman
2025-06-26 22:42 ` [PATCH v10 16/17] CXL/PCI: Enable CXL protocol errors during CXL Port probe Terry Bowman
2025-06-26 22:42 ` [PATCH v10 17/17] CXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup Terry Bowman
2025-07-23 21:55 ` [PATCH v10 00/17] Enable CXL PCIe Port Protocol Error handling and logging dan.j.williams
2025-07-24 15:58 ` Bowman, Terry
2025-08-18 15:18 ` Joshua Hahn
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=6882964d627d8_134cc710044@dwillia2-xfh.jf.intel.com.notmuch \
--to=dan.j.williams@intel.com \
--cc=Benjamin.Cheatham@amd.com \
--cc=PradeepVineshReddy.Kodamati@amd.com \
--cc=Smita.KoralahalliChannabasappa@amd.com \
--cc=alison.schofield@intel.com \
--cc=bhelgaas@google.com \
--cc=dan.carpenter@linaro.org \
--cc=dave.jiang@intel.com \
--cc=dave@stgolabs.net \
--cc=jonathan.cameron@huawei.com \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lukas@wunner.de \
--cc=ming.li@zohomail.com \
--cc=rrichter@amd.com \
--cc=sathyanarayanan.kuppuswamy@linux.intel.com \
--cc=shiju.jose@huawei.com \
--cc=terry.bowman@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).