From: Ira Weiny <ira.weiny@intel.com>
To: Dave Jiang <dave.jiang@intel.com>,
Ira Weiny <ira.weiny@intel.com>, <linux-cxl@vger.kernel.org>
Cc: <dave@stgolabs.net>, <jonathan.cameron@huawei.com>,
<alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<dan.j.williams@intel.com>, Robert Richter <rrichter@amd.com>
Subject: Re: [PATCH] cxl: Move port register setup to when first dport appear
Date: Thu, 18 Sep 2025 16:28:59 -0500 [thread overview]
Message-ID: <68cc799b60225_194a3e29483@iweiny-mobl.notmuch> (raw)
In-Reply-To: <b928abb5-17bb-4c6c-863c-5f32db3b07d5@intel.com>
Dave Jiang wrote:
>
>
> On 9/18/25 12:30 PM, Ira Weiny wrote:
> > Dave Jiang wrote:
> >
> > [snip]
> >
> >>
> >> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> >> index 76dd06d282df..416d45516d82 100644
> >> --- a/drivers/cxl/core/port.c
> >> +++ b/drivers/cxl/core/port.c
> >> @@ -867,9 +867,7 @@ static int cxl_port_add(struct cxl_port *port,
> >> if (rc)
> >> return rc;
> >>
> >> - rc = cxl_port_setup_regs(port, component_reg_phys);
> >> - if (rc)
> >> - return rc;
> >> + port->component_reg_phys = component_reg_phys;
> >> } else {
> >> rc = dev_set_name(dev, "root%d", port->id);
> >> if (rc)
> >> @@ -1200,6 +1198,18 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
> >>
> >> cxl_debugfs_create_dport_dir(dport);
> >>
> >> + /*
> >> + * Setup port register if this is the first dport showed up. Having
> >> + * a dport also means that there is at least 1 active link.
> >> + */
> >> + if (port->nr_dports == 1 &&
> >> + port->component_reg_phys != CXL_RESOURCE_NONE) {
> >
> > Should this be
> > port->component_reg_phys == CXL_RESOURCE_NONE) {
> > ^^
> > ?
> >
> > to match with
> >
> > /* Note: endpoint port component registers are derived from @cxlds */
> > endpoint = devm_cxl_add_port(host, &cxlmd->dev, CXL_RESOURCE_NONE,
> > parent_dport);
> >
> > in the memdev probe path?
>
>
> No. port->component_reg_phys gets set in cxl_port_add(). So by the time the first dport shows up, we are using it to setup the register and then setting that back to CXL_RESOURCE_NONE. So therefore the port probe happens when it's the first dport and port->component_reg_phys is a valid address.
>
Ok I see it now. yes I was not thinking correctly in that the acpi path
is setting the component_reg_phys and it is being saved for later...
All is good now.
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
[snip]
next prev parent reply other threads:[~2025-09-18 21:27 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-11 20:44 [PATCH] cxl: Move port register setup to when first dport appear Dave Jiang
2025-09-18 18:05 ` Alison Schofield
2025-09-18 19:30 ` Ira Weiny
2025-09-18 21:05 ` Dave Jiang
2025-09-18 21:28 ` Ira Weiny [this message]
2025-09-18 22:07 ` Dave Jiang
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