Re: [PATCH 1/5] PCI: Add CXL DVSEC control, lock, and range register definitions

Vishal Aslot
2026-03-16T14:03:00Z

I am wondering..thinking out loud here..what if the cxl "driver" (e.g the port driver) registered for its own "reset_prep" and "reset_done"? Or would having the cxl specific routine in cxl driver that pcie reset path calls into work? I realize the 2nd suggestion may not address the main concern but it's an improvement.

-Vishal
________________________________________
From: Dan Williams <dan.j.williams@intel.com>
Sent: Tuesday, March 10, 2026 4:44 PM
To: Srirangan Madhavan; bhelgaas@google.com; dan.j.williams@intel.com; dave.jiang@intel.com; jonathan.cameron@huawei.com; ira.weiny@intel.com; vishal.l.verma@intel.com; alison.schofield@intel.com; dave@stgolabs.net
Cc: Alex Williamson; Jeshua Smith; Vikram Sethi; Sai Yashwanth Reddy Kancherla; Vishal Aslot; Shanker Donthineni; Manish Honap; Vidya Sagar; Jiandi An; Matt Ochs; Derek Schumacher; linux-cxl@vger.kernel.org; linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org; Srirangan Madhavan
Subject: Re: [PATCH 1/5] PCI: Add CXL DVSEC control, lock, and range register definitions

External email: Use caution opening links or attachments

smadhavan@ wrote:
> From: Srirangan Madhavan <smadhavan@nvidia.com>
>
> PCI: Add CXL DVSEC control, lock, and range register definitions
>
> Add register offset and field definitions for CXL DVSEC registers needed
> by CXL state save/restore across resets:
>
> - CTRL2 (offset 0x10) and LOCK (offset 0x14) registers
> - CONFIG_LOCK bit in the LOCK register
> - RWL (read-write-when-locked) field masks for CTRL and range base
> registers.
>
> Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
> ---
> include/uapi/linux/pci_regs.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index ec1c54b5a310..6fdc20d7f5e6 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -1353,14 +1353,20 @@
> #define PCI_DVSEC_CXL_HDM_COUNT __GENMASK(5, 4)
> #define PCI_DVSEC_CXL_CTRL 0xC
> #define PCI_DVSEC_CXL_MEM_ENABLE _BITUL(2)
> +#define PCI_DVSEC_CXL_CTRL_RWL 0x5FED

This is odd, why is it needed? If the bits are locked then writes are
dropped.