[PATCH 1/5] PCI: Add CXL DVSEC control, lock, and range register definitions

smadhavan
2026-03-06T08:00:58Z

From: Srirangan Madhavan <smadhavan@nvidia.com>

PCI: Add CXL DVSEC control, lock, and range register definitions

Add register offset and field definitions for CXL DVSEC registers needed
by CXL state save/restore across resets:

- CTRL2 (offset 0x10) and LOCK (offset 0x14) registers
- CONFIG_LOCK bit in the LOCK register
- RWL (read-write-when-locked) field masks for CTRL and range base
registers.

Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
---
include/uapi/linux/pci_regs.h | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index ec1c54b5a310..6fdc20d7f5e6 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1353,14 +1353,20 @@
#define PCI_DVSEC_CXL_HDM_COUNT __GENMASK(5, 4)
#define PCI_DVSEC_CXL_CTRL 0xC
#define PCI_DVSEC_CXL_MEM_ENABLE _BITUL(2)
+#define PCI_DVSEC_CXL_CTRL_RWL 0x5FED
+#define PCI_DVSEC_CXL_CTRL2 0x10
+#define PCI_DVSEC_CXL_LOCK 0x14
+#define PCI_DVSEC_CXL_LOCK_CONFIG _BITUL(0)
#define PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10))
#define PCI_DVSEC_CXL_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10))
#define PCI_DVSEC_CXL_MEM_INFO_VALID _BITUL(0)
#define PCI_DVSEC_CXL_MEM_ACTIVE _BITUL(1)
#define PCI_DVSEC_CXL_MEM_SIZE_LOW __GENMASK(31, 28)
#define PCI_DVSEC_CXL_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10))
+#define PCI_DVSEC_CXL_RANGE_BASE_HI_RWL 0xFFFFFFFF
#define PCI_DVSEC_CXL_RANGE_BASE_LOW(i) (0x24 + (i * 0x10))
#define PCI_DVSEC_CXL_MEM_BASE_LOW __GENMASK(31, 28)
+#define PCI_DVSEC_CXL_RANGE_BASE_LO_RWL 0xF0000000

#define CXL_DVSEC_RANGE_MAX 2

--
2.43.0