From: "Dan Williams (nvidia)" <djbw@kernel.org>
To: sashiko-bot@kernel.org, alejandro.lucero-palau@amd.com
Cc: linux-cxl@vger.kernel.org
Subject: Re: [PATCH v29 4/5] sfc: obtain and map cxl range using devm_cxl_probe_mem
Date: Wed, 24 Jun 2026 14:45:32 -0700 [thread overview]
Message-ID: <6a3c4ffc36c36_f123010054@djbw-dev.notmuch> (raw)
In-Reply-To: <20260623124055.291BB1F000E9@smtp.kernel.org>
sashiko-bot@ wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [High] Resource Teardown Ordering Violation in efx_pci_remove
> - [High] Missing Hardware State Restoration for CXL HDM Decoders After FLR
> --
>
> commit cd561fb9993e195accb646b7a8524a13a2dd0b79
> Author: Alejandro Lucero <alucerop@amd.com>
> Subject: sfc: obtain and map cxl range using devm_cxl_probe_mem
>
> This commit introduces CXL support to the sfc driver by creating a CXL
> memory device using devm_cxl_probe_mem() and mapping the CXL range for
> CTPIO buffer usage.
>
> > diff --git a/drivers/net/ethernet/sfc/efx.c b/drivers/net/ethernet/sfc/efx.c
> > --- a/drivers/net/ethernet/sfc/efx.c
> > +++ b/drivers/net/ethernet/sfc/efx.c
> > @@ -984,6 +984,7 @@ static void efx_pci_remove(struct pci_dev *pci_dev)
> > efx_fini_io(efx);
> >
> > probe_data = container_of(efx, struct efx_probe_data, efx);
> > + efx_cxl_exit(probe_data);
>
> [Severity: High]
> Does this tear down resources in the correct order?
>
> efx_fini_io() calls pci_disable_device() which disables memory decoding for
> the endpoint.
>
> Because the CXL memdev and its sysfs interfaces are managed by devres
> (created via devm_cxl_probe_mem() during probe), they remain active until
> devres_release_all() runs after efx_pci_remove() returns.
>
> If userspace (e.g., CXL utilities, udev) accesses the CXL sysfs attributes
> in this window, the CXL core will attempt to read memory-mapped component
> registers on the disabled device.
>
> Could this result in PCIe Unsupported Requests (UR) and a fatal AER fault or
> kernel panic?
>
> >
> > pci_dbg(efx->pci_dev, "shutdown successful\n");
>
> [ ... ]
>
> > diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
> > --- a/drivers/net/ethernet/sfc/efx_cxl.c
> > +++ b/drivers/net/ethernet/sfc/efx_cxl.c
>
> [ ... ]
>
> > @@ -73,9 +74,31 @@ int efx_cxl_init(struct efx_probe_data *probe_data)
> > return -ENODEV;
> > }
> >
> > + cxl->cxlmd = devm_cxl_probe_mem(&cxl->cxlds, &cxl_pio_range);
>
> [Severity: High]
> Is there a mechanism to restore the CXL HDM decoders after a Function Level
> Reset (FLR)?
FLR does not impact CXL settings.
next prev parent reply other threads:[~2026-06-24 21:45 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-22 12:40 [PATCH v29 0/5] Type2 device basic support alejandro.lucero-palau
2026-06-22 12:40 ` [PATCH v29 1/5] sfc: add cxl support alejandro.lucero-palau
2026-06-22 12:40 ` [PATCH v29 2/5] cxl/sfc: Map cxl regs alejandro.lucero-palau
2026-06-23 12:40 ` sashiko-bot
2026-06-24 21:59 ` Dan Williams (nvidia)
2026-06-22 12:40 ` [PATCH v29 3/5] cxl/sfc: Initialize dpa without a mailbox alejandro.lucero-palau
2026-06-22 12:40 ` [PATCH v29 4/5] sfc: obtain and map cxl range using devm_cxl_probe_mem alejandro.lucero-palau
2026-06-23 12:40 ` sashiko-bot
2026-06-24 21:45 ` Dan Williams (nvidia) [this message]
2026-06-24 22:10 ` Dan Williams (nvidia)
2026-06-25 9:31 ` Alejandro Lucero Palau
2026-06-25 20:34 ` Dan Williams (nvidia)
2026-06-26 3:52 ` Richard Cheng
2026-06-29 13:20 ` Alejandro Lucero Palau
2026-06-30 9:31 ` Richard Cheng
2026-06-22 12:40 ` [PATCH v29 5/5] sfc: support pio mapping based on cxl alejandro.lucero-palau
2026-06-23 12:40 ` sashiko-bot
2026-06-26 3:56 ` [PATCH v29 0/5] Type2 device basic support Richard Cheng
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