From: Dave Jiang <dave.jiang@intel.com>
To: Richard Cheng <icheng@nvidia.com>,
Srirangan Madhavan <smadhavan@nvidia.com>
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, vsethi@nvidia.com,
alwilliamson@nvidia.com, Dan Williams <danwilliams@nvidia.com>,
Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
Vishal Aslot <vaslot@nvidia.com>,
Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
linux-tegra@vger.kernel.org
Subject: Re: [PATCH v6 1/9] cxl/hdm: Add helpers to restore and commit memdev decoders
Date: Tue, 2 Jun 2026 11:12:42 -0700 [thread overview]
Message-ID: <79fbf3fc-81ce-45c3-9889-be4c3867bfb8@intel.com> (raw)
In-Reply-To: <ahghCNiphEn6X8gn@MWDK4CY14F>
On 5/28/26 4:06 AM, Richard Cheng wrote:
> On Thu, May 28, 2026 at 08:31:46AM +0800, Srirangan Madhavan wrote:
<-- snip -->
>> +static int cxl_restore_dvsec_range(struct cxl_memdev *cxlmd,
>> + struct cxl_endpoint_decoder *cxled)
>> +{
>> + struct cxl_dev_state *cxlds = cxlmd->cxlds;
>> + struct cxl_decoder *cxld = &cxled->cxld;
>> + struct pci_dev *pdev = to_pci_dev(cxlds->dev);
>> + u64 base = cxld->hpa_range.start;
>> + u64 size = range_len(&cxld->hpa_range);
>> + u32 lo;
>> + int dvsec = cxlds->cxl_dvsec;
>> + int id = cxld->id;
>> + int rc;
>> +
>> + if (!dvsec)
>> + return 0;
>> +
>> + if (id >= CXL_DVSEC_RANGE_MAX)
>> + return 0;
>> +
>> + rc = pci_write_config_dword(pdev, dvsec + PCI_DVSEC_CXL_RANGE_BASE_HIGH(id),
>> + upper_32_bits(base));
>> + if (rc)
>> + return rc;
>> +
>> + rc = pci_read_config_dword(pdev, dvsec + PCI_DVSEC_CXL_RANGE_BASE_LOW(id),
>> + &lo);
>> + if (rc)
>> + return rc;
>
> Here pci_read/write* returns positive values on failure, and you pass the value up.
> Eventually surfacing through cxl_reset_store to userspace where sysfs thinks positive
> values as "bytes written".
>
> I think this might need a fix ?
Great catch! Not something I ever thought about before WRT pci_read/write*. I think to get errno it needs pcibios_err_to_errno() wrapper called. The sysfs exposure definitely needs to be audited.
next prev parent reply other threads:[~2026-06-02 18:12 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-28 8:31 [PATCH v6 0/9] cxl: Add cxl_reset sysfs attribute for memdevs Srirangan Madhavan
2026-05-28 8:31 ` [PATCH v6 1/9] cxl/hdm: Add helpers to restore and commit memdev decoders Srirangan Madhavan
2026-05-28 11:06 ` Richard Cheng
2026-06-02 18:12 ` Dave Jiang [this message]
2026-06-02 18:31 ` Dave Jiang
2026-06-02 20:34 ` Cheatham, Benjamin
2026-06-03 22:35 ` Dan Williams (nvidia)
2026-05-28 8:31 ` [PATCH v6 2/9] PCI: Export pci_dev_save_and_disable() and pci_dev_restore() Srirangan Madhavan
2026-06-02 20:18 ` Dave Jiang
2026-06-03 22:36 ` Dan Williams (nvidia)
2026-05-28 8:31 ` [PATCH v6 3/9] cxl: Add reset-idle and cache flush helpers Srirangan Madhavan
2026-06-02 20:34 ` Cheatham, Benjamin
2026-06-02 20:36 ` Dave Jiang
2026-06-04 2:49 ` Dan Williams (nvidia)
2026-05-28 8:31 ` [PATCH v6 4/9] PCI/CXL: Add sibling function coordination for reset Srirangan Madhavan
2026-05-28 11:15 ` Richard Cheng
2026-06-02 22:10 ` Dave Jiang
2026-06-04 3:13 ` Dan Williams (nvidia)
2026-05-28 8:31 ` [PATCH v6 5/9] cxl/pci: Add CXL DVSEC reset helper Srirangan Madhavan
2026-06-02 20:34 ` Cheatham, Benjamin
2026-05-28 8:31 ` [PATCH v6 6/9] cxl/pci: Track memdevs affected by CXL reset Srirangan Madhavan
2026-06-02 20:34 ` Cheatham, Benjamin
2026-05-28 8:31 ` [PATCH v6 7/9] cxl/pci: Orchestrate CXL reset for affected memdevs Srirangan Madhavan
2026-06-02 20:34 ` Cheatham, Benjamin
2026-06-04 3:25 ` Dan Williams (nvidia)
2026-05-28 8:31 ` [PATCH v6 8/9] cxl/memdev: Add cxl_reset sysfs attribute Srirangan Madhavan
2026-06-02 21:35 ` Cheatham, Benjamin
2026-06-02 23:50 ` Dave Jiang
2026-05-28 8:31 ` [PATCH v6 9/9] Documentation/ABI: Document CXL memdev cxl_reset Srirangan Madhavan
2026-06-03 0:11 ` Dave Jiang
2026-06-02 20:34 ` [PATCH v6 0/9] cxl: Add cxl_reset sysfs attribute for memdevs Cheatham, Benjamin
2026-06-02 21:42 ` Dan Williams (nvidia)
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