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Tsirkin" , Igor Mammedov , linux-cxl@vger.kernel.org, Ben Widawsky , Peter Maydell , linuxarm@huawei.com, Shameerali Kolothum Thodi , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Saransh Gupta1 , Shreyas Shah , Chris Browy , Samarth Saxena , Dan Williams Subject: Re: [PATCH v6 21/43] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Date: Wed, 02 Mar 2022 10:01:48 +0000 In-reply-to: <20220211120747.3074-22-Jonathan.Cameron@huawei.com> Message-ID: <871qzkllj1.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Jonathan Cameron writes: > From: Ben Widawsky > > This should introduce no change. Subsequent work will make use of this > new class member. > > Signed-off-by: Ben Widawsky > Signed-off-by: Jonathan Cameron > --- > hw/cxl/cxl-mailbox-utils.c | 3 +++ > hw/mem/cxl_type3.c | 24 +++++++++--------------- > include/hw/cxl/cxl_device.h | 29 +++++++++++++++++++++++++++++ > 3 files changed, 41 insertions(+), 15 deletions(-) > > diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c > index d022711b2a..ccf9c3d794 100644 > --- a/hw/cxl/cxl-mailbox-utils.c > +++ b/hw/cxl/cxl-mailbox-utils.c > @@ -278,6 +278,8 @@ static ret_code cmd_identify_memory_device(struct cxl= _cmd *cmd, > } __attribute__((packed)) *id; > _Static_assert(sizeof(*id) =3D=3D 0x43, "Bad identify size"); >=20=20 > + CXLType3Dev *ct3d =3D container_of(cxl_dstate, CXLType3Dev, cxl_dsta= te); > + CXLType3Class *cvc =3D CXL_TYPE3_DEV_GET_CLASS(ct3d); > uint64_t size =3D cxl_dstate->pmem_size; >=20=20 > if (!QEMU_IS_ALIGNED(size, 256 << 20)) { > @@ -292,6 +294,7 @@ static ret_code cmd_identify_memory_device(struct cxl= _cmd *cmd, >=20=20 > id->total_capacity =3D size / (256 << 20); > id->persistent_capacity =3D size / (256 << 20); > + id->lsa_size =3D cvc->get_lsa_size(ct3d); >=20=20 > *len =3D sizeof(*id); > return CXL_MBOX_SUCCESS; > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c > index da091157f2..b16262d3cc 100644 > --- a/hw/mem/cxl_type3.c > +++ b/hw/mem/cxl_type3.c > @@ -13,21 +13,6 @@ > #include "sysemu/hostmem.h" > #include "hw/cxl/cxl.h" >=20=20 > -typedef struct cxl_type3_dev { > - /* Private */ > - PCIDevice parent_obj; > - > - /* Properties */ > - uint64_t size; > - HostMemoryBackend *hostmem; > - > - /* State */ > - CXLComponentState cxl_cstate; > - CXLDeviceState cxl_dstate; > -} CXLType3Dev; > - > -#define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV) > - If the structure had been in the header to start with it would be easier to see the changes added for this bit. > static void build_dvsecs(CXLType3Dev *ct3d) > { > CXLComponentState *cxl_cstate =3D &ct3d->cxl_cstate; > @@ -186,10 +171,16 @@ static Property ct3_props[] =3D { > DEFINE_PROP_END_OF_LIST(), > }; >=20=20 > +static uint64_t get_lsa_size(CXLType3Dev *ct3d) > +{ > + return 0; > +} > + > static void ct3_class_init(ObjectClass *oc, void *data) > { > DeviceClass *dc =3D DEVICE_CLASS(oc); > PCIDeviceClass *pc =3D PCI_DEVICE_CLASS(oc); > + CXLType3Class *cvc =3D CXL_TYPE3_DEV_CLASS(oc); >=20=20 > pc->realize =3D ct3_realize; > pc->class_id =3D PCI_CLASS_STORAGE_EXPRESS; > @@ -201,11 +192,14 @@ static void ct3_class_init(ObjectClass *oc, void *d= ata) > dc->desc =3D "CXL PMEM Device (Type 3)"; > dc->reset =3D ct3d_reset; > device_class_set_props(dc, ct3_props); > + > + cvc->get_lsa_size =3D get_lsa_size; > } >=20=20 > static const TypeInfo ct3d_info =3D { > .name =3D TYPE_CXL_TYPE3_DEV, > .parent =3D TYPE_PCI_DEVICE, > + .class_size =3D sizeof(struct CXLType3Class), > .class_init =3D ct3_class_init, > .instance_size =3D sizeof(CXLType3Dev), > .instance_finalize =3D ct3_finalize, > diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h > index 8102d2a813..ebb391153a 100644 > --- a/include/hw/cxl/cxl_device.h > +++ b/include/hw/cxl/cxl_device.h > @@ -230,4 +230,33 @@ REG64(CXL_MEM_DEV_STS, 0) > FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1) > FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3) >=20=20 > +typedef struct cxl_type3_dev { > + /* Private */ > + PCIDevice parent_obj; > + > + /* Properties */ > + uint64_t size; > + HostMemoryBackend *hostmem; > + HostMemoryBackend *lsa; > + > + /* State */ > + CXLComponentState cxl_cstate; > + CXLDeviceState cxl_dstate; > +} CXLType3Dev; > + > +#ifndef TYPE_CXL_TYPE3_DEV > +#define TYPE_CXL_TYPE3_DEV "cxl-type3" > +#endif > + > +#define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV) > +OBJECT_DECLARE_TYPE(CXLType3Device, CXLType3Class, CXL_TYPE3_DEV) > + > +struct CXLType3Class { > + /* Private */ > + PCIDeviceClass parent_class; > + > + /* public */ > + uint64_t (*get_lsa_size)(CXLType3Dev *ct3d); > +}; > + > #endif --=20 Alex Benn=C3=A9e