* [PATCH qemu v4 1/7] hw/cxl/events: Update for rev3.2 common event record format
2025-07-21 17:22 [PATCH qemu v4 0/7] hw/cxl: Update CXL events to rev3.2 and add maintenance support for memory repair features shiju.jose
@ 2025-07-21 17:22 ` shiju.jose
2025-07-25 12:45 ` Jonathan Cameron
2025-08-06 7:45 ` Markus Armbruster
2025-07-21 17:22 ` [PATCH qemu v4 2/7] hw/cxl/events: Updates for rev3.2 general media event record shiju.jose
` (5 subsequent siblings)
6 siblings, 2 replies; 17+ messages in thread
From: shiju.jose @ 2025-07-21 17:22 UTC (permalink / raw)
To: qemu-devel, linux-cxl, jonathan.cameron, fan.ni, dave
Cc: linuxarm, shiju.jose
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
format has updated with optional Maintenance Operation Subclass,
LD ID and ID of the device head information.
Add updates for the above optional parameters in the related
CXL events reporting and in the QMP commands to inject CXL events.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
hw/cxl/cxl-events.c | 3 +-
hw/cxl/cxl-mailbox-utils.c | 3 +-
hw/mem/cxl_type3.c | 70 ++++++++++++++++++++++++++++++++-----
hw/mem/cxl_type3_stubs.c | 24 +++++++++++--
include/hw/cxl/cxl_device.h | 7 +++-
include/hw/cxl/cxl_events.h | 15 ++++++--
qapi/cxl.json | 48 +++++++++++++++++++++++--
7 files changed, 150 insertions(+), 20 deletions(-)
diff --git a/hw/cxl/cxl-events.c b/hw/cxl/cxl-events.c
index 724055f2cf..673154db29 100644
--- a/hw/cxl/cxl-events.c
+++ b/hw/cxl/cxl-events.c
@@ -273,7 +273,8 @@ void cxl_create_dc_event_records_for_extents(CXLType3Dev *ct3d,
&dynamic_capacity_uuid,
(1 << CXL_EVENT_TYPE_INFO),
sizeof(event_rec),
- cxl_device_get_timestamp(&ct3d->cxl_dstate));
+ cxl_device_get_timestamp(&ct3d->cxl_dstate),
+ 0, 0, 0, 0, 0, 0, 0, 0);
event_rec.type = type;
event_rec.validity_flags = 1;
event_rec.host_id = 0;
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 43a0d503aa..8f62ea9b54 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -3457,7 +3457,8 @@ static CXLRetCode cmd_fm_set_dc_region_config(const struct cxl_cmd *cmd,
&dynamic_capacity_uuid,
(1 << CXL_EVENT_TYPE_INFO),
sizeof(dcEvent),
- cxl_device_get_timestamp(&ct3d->cxl_dstate));
+ cxl_device_get_timestamp(&ct3d->cxl_dstate),
+ 0, 0, 0, 0, 0, 0, 0, 0);
dcEvent.type = DC_EVENT_REGION_CONFIG_UPDATED;
dcEvent.validity_flags = 1;
dcEvent.host_id = 0;
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 7676d785c2..aa6e5c1a08 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1592,12 +1592,39 @@ void qmp_cxl_inject_correctable_error(const char *path, CxlCorErrorType type,
void cxl_assign_event_header(CXLEventRecordHdr *hdr,
const QemuUUID *uuid, uint32_t flags,
- uint8_t length, uint64_t timestamp)
+ uint8_t length, uint64_t timestamp,
+ bool has_maint_op_class, uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id)
{
- st24_le_p(&hdr->flags, flags);
hdr->length = length;
memcpy(&hdr->id, uuid, sizeof(hdr->id));
stq_le_p(&hdr->timestamp, timestamp);
+
+ if (has_maint_op_class) {
+ hdr->maint_op_class = maint_op_class;
+ } else {
+ hdr->maint_op_class = 0;
+ }
+
+ if (has_maint_op_subclass) {
+ flags |= CXL_EVENT_REC_FLAGS_MAINT_OP_SUBCLASS_VALID;
+ hdr->maint_op_subclass = maint_op_subclass;
+ }
+
+ if (has_ld_id) {
+ flags |= CXL_EVENT_REC_FLAGS_LD_ID_VALID;
+ stw_le_p(&hdr->ld_id, ld_id);
+ }
+
+ if (has_head_id) {
+ flags |= CXL_EVENT_REC_FLAGS_HEAD_ID_VALID;
+ hdr->head_id = head_id;
+ }
+
+ st24_le_p(&hdr->flags, flags);
}
static const QemuUUID gen_media_uuid = {
@@ -1637,7 +1664,13 @@ static int ct3d_qmp_cxl_event_log_enc(CxlEventLog log)
}
/* Component ID is device specific. Define this as a string. */
void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
- uint8_t flags, uint64_t dpa,
+ uint32_t flags, bool has_maint_op_class,
+ uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
+ uint64_t dpa,
uint8_t descriptor, uint8_t type,
uint8_t transaction_type,
bool has_channel, uint8_t channel,
@@ -1675,7 +1708,10 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
memset(&gem, 0, sizeof(gem));
cxl_assign_event_header(hdr, &gen_media_uuid, flags, sizeof(gem),
- cxl_device_get_timestamp(&ct3d->cxl_dstate));
+ cxl_device_get_timestamp(&ct3d->cxl_dstate),
+ has_maint_op_class, maint_op_class,
+ has_maint_op_subclass, maint_op_subclass,
+ has_ld_id, ld_id, has_head_id, head_id);
stq_le_p(&gem.phys_addr, dpa);
gem.descriptor = descriptor;
@@ -1719,7 +1755,13 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
#define CXL_DRAM_VALID_COLUMN BIT(6)
#define CXL_DRAM_VALID_CORRECTION_MASK BIT(7)
-void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
+void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
+ uint32_t flags,
+ bool has_maint_op_class, uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
uint64_t dpa, uint8_t descriptor,
uint8_t type, uint8_t transaction_type,
bool has_channel, uint8_t channel,
@@ -1762,7 +1804,10 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
memset(&dram, 0, sizeof(dram));
cxl_assign_event_header(hdr, &dram_uuid, flags, sizeof(dram),
- cxl_device_get_timestamp(&ct3d->cxl_dstate));
+ cxl_device_get_timestamp(&ct3d->cxl_dstate),
+ has_maint_op_class, maint_op_class,
+ has_maint_op_subclass, maint_op_subclass,
+ has_ld_id, ld_id, has_head_id, head_id);
stq_le_p(&dram.phys_addr, dpa);
dram.descriptor = descriptor;
dram.type = type;
@@ -1822,7 +1867,13 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
}
void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
- uint8_t flags, uint8_t type,
+ uint32_t flags, bool has_maint_op_class,
+ uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
+ uint8_t type,
uint8_t health_status,
uint8_t media_status,
uint8_t additional_status,
@@ -1861,7 +1912,10 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
memset(&module, 0, sizeof(module));
cxl_assign_event_header(hdr, &memory_module_uuid, flags, sizeof(module),
- cxl_device_get_timestamp(&ct3d->cxl_dstate));
+ cxl_device_get_timestamp(&ct3d->cxl_dstate),
+ has_maint_op_class, maint_op_class,
+ has_maint_op_subclass, maint_op_subclass,
+ has_ld_id, ld_id, has_head_id, head_id);
module.type = type;
module.health_status = health_status;
diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
index c1a5e4a7c1..91b1478114 100644
--- a/hw/mem/cxl_type3_stubs.c
+++ b/hw/mem/cxl_type3_stubs.c
@@ -14,7 +14,13 @@
#include "qapi/qapi-commands-cxl.h"
void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
- uint8_t flags, uint64_t dpa,
+ uint32_t flags, bool has_maint_op_class,
+ uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
+ uint64_t dpa,
uint8_t descriptor, uint8_t type,
uint8_t transaction_type,
bool has_channel, uint8_t channel,
@@ -23,7 +29,13 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
const char *component_id,
Error **errp) {}
-void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
+void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
+ uint32_t flags,
+ bool has_maint_op_class, uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
uint64_t dpa, uint8_t descriptor,
uint8_t type, uint8_t transaction_type,
bool has_channel, uint8_t channel,
@@ -38,7 +50,13 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
Error **errp) {}
void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
- uint8_t flags, uint8_t type,
+ uint32_t flags, bool has_maint_op_class,
+ uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id,
+ uint8_t type,
uint8_t health_status,
uint8_t media_status,
uint8_t additional_status,
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index fdee60b977..b77b6b2499 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -723,7 +723,12 @@ bool ct3_test_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,
uint64_t len);
void cxl_assign_event_header(CXLEventRecordHdr *hdr,
const QemuUUID *uuid, uint32_t flags,
- uint8_t length, uint64_t timestamp);
+ uint8_t length, uint64_t timestamp,
+ bool has_maint_op_class, uint8_t maint_op_class,
+ bool has_maint_op_subclass,
+ uint8_t maint_op_subclass,
+ bool has_ld_id, uint16_t ld_id,
+ bool has_head_id, uint8_t head_id);
void cxl_create_dc_event_records_for_extents(CXLType3Dev *ct3d,
CXLDCEventType type,
CXLDCExtentRaw extents[],
diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
index 758b075a64..4d9cfdb621 100644
--- a/include/hw/cxl/cxl_events.h
+++ b/include/hw/cxl/cxl_events.h
@@ -29,9 +29,15 @@ typedef enum CXLEventLogType {
/*
* Common Event Record Format
- * CXL r3.1 section 8.2.9.2.1: Event Records; Table 8-43
+ * CXL r3.2 section 8.2.10.2.1: Event Records; Table 8-55
*/
-#define CXL_EVENT_REC_HDR_RES_LEN 0xf
+#define CXL_EVENT_REC_FLAGS_PERMANENT_COND BIT(2)
+#define CXL_EVENT_REC_FLAGS_MAINT_NEEDED BIT(3)
+#define CXL_EVENT_REC_FLAGS_PERF_DEGRADED BIT(4)
+#define CXL_EVENT_REC_FLAGS_HW_REPLACEMENT_NEEDED BIT(5)
+#define CXL_EVENT_REC_FLAGS_MAINT_OP_SUBCLASS_VALID BIT(6)
+#define CXL_EVENT_REC_FLAGS_LD_ID_VALID BIT(7)
+#define CXL_EVENT_REC_FLAGS_HEAD_ID_VALID BIT(8)
typedef struct CXLEventRecordHdr {
QemuUUID id;
uint8_t length;
@@ -40,7 +46,10 @@ typedef struct CXLEventRecordHdr {
uint16_t related_handle;
uint64_t timestamp;
uint8_t maint_op_class;
- uint8_t reserved[CXL_EVENT_REC_HDR_RES_LEN];
+ uint8_t maint_op_subclass;
+ uint16_t ld_id;
+ uint8_t head_id;
+ uint8_t reserved[0xb];
} QEMU_PACKED CXLEventRecordHdr;
#define CXL_EVENT_RECORD_DATA_LENGTH 0x50
diff --git a/qapi/cxl.json b/qapi/cxl.json
index 8f2e9237b1..c1fe8319c8 100644
--- a/qapi/cxl.json
+++ b/qapi/cxl.json
@@ -42,6 +42,18 @@
# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
# Record Format, Event Record Flags for subfield definitions.
#
+# @maint-op-class: Maintenance operation class the device requests to initiate.
+# See CXL r3.2 Table 8-55 Common Event Record Format.
+#
+# @maint-op-subclass: Maintenance operation subclass the device requests to
+# initiate. See CXL r3.2 Table 8-55 Common Event Record Format.
+#
+# @ld-id: LD ID of LD from where the event originated.
+# See CXL r3.2 Table 8-55 Common Event Record Format.
+#
+# @head-id: ID of the device head from where the event originated.
+# See CXL r3.2 Table 8-55 Common Event Record Format.
+#
# @dpa: Device Physical Address (relative to @path device). Note
# lower bits include some flags. See CXL r3.0 Table 8-43 General
# Media Event Record, Physical Address.
@@ -73,7 +85,9 @@
# Since: 8.1
##
{ 'command': 'cxl-inject-general-media-event',
- 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
+ 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint32',
+ '*maint-op-class':'uint8', '*maint-op-subclass':'uint8',
+ '*ld-id':'uint16', '*head-id':'uint8',
'dpa': 'uint64', 'descriptor': 'uint8',
'type': 'uint8', 'transaction-type': 'uint8',
'*channel': 'uint8', '*rank': 'uint8',
@@ -93,6 +107,18 @@
# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
# Record Format, Event Record Flags for subfield definitions.
#
+# @maint-op-class: Maintenance operation class the device requests to initiate.
+# See CXL r3.2 Table 8-55 Common Event Record Format.
+#
+# @maint-op-subclass: Maintenance operation subclass the device requests to
+# initiate. See CXL r3.2 Table 8-55 Common Event Record Format.
+#
+# @ld-id: LD ID of LD from where the event originated.
+# See CXL r3.2 Table 8-55 Common Event Record Format.
+#
+# @head-id: ID of the device head from where the event originated.
+# See CXL r3.2 Table 8-55 Common Event Record Format.
+#
# @dpa: Device Physical Address (relative to @path device). Note
# lower bits include some flags. See CXL r3.0 Table 8-44 DRAM
# Event Record, Physical Address.
@@ -132,7 +158,9 @@
# Since: 8.1
##
{ 'command': 'cxl-inject-dram-event',
- 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
+ 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint32',
+ '*maint-op-class':'uint8', '*maint-op-subclass':'uint8',
+ '*ld-id':'uint16', '*head-id':'uint8',
'dpa': 'uint64', 'descriptor': 'uint8',
'type': 'uint8', 'transaction-type': 'uint8',
'*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
@@ -154,6 +182,18 @@
# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
# Record Format, Event Record Flags for subfield definitions.
#
+# @maint-op-class: Maintenance operation class the device requests to initiate.
+# See CXL r3.2 Table 8-55 Common Event Record Format.
+#
+# @maint-op-subclass: Maintenance operation subclass the device requests to
+# initiate. See CXL r3.2 Table 8-55 Common Event Record Format.
+#
+# @ld-id: LD ID of LD from where the event originated.
+# See CXL r3.2 Table 8-55 Common Event Record Format.
+#
+# @head-id: ID of the device head from where the event originated.
+# See CXL r3.2 Table 8-55 Common Event Record Format.
+#
# @type: Device Event Type. See CXL r3.0 Table 8-45 Memory Module
# Event Record for bit definitions for bit definiions.
#
@@ -184,7 +224,9 @@
# Since: 8.1
##
{ 'command': 'cxl-inject-memory-module-event',
- 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags' : 'uint8',
+ 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags' : 'uint32',
+ '*maint-op-class':'uint8', '*maint-op-subclass':'uint8',
+ '*ld-id':'uint16', '*head-id':'uint8',
'type': 'uint8', 'health-status': 'uint8',
'media-status': 'uint8', 'additional-status': 'uint8',
'life-used': 'uint8', 'temperature' : 'int16',
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH qemu v4 1/7] hw/cxl/events: Update for rev3.2 common event record format
2025-07-21 17:22 ` [PATCH qemu v4 1/7] hw/cxl/events: Update for rev3.2 common event record format shiju.jose
@ 2025-07-25 12:45 ` Jonathan Cameron
2025-08-06 7:45 ` Markus Armbruster
1 sibling, 0 replies; 17+ messages in thread
From: Jonathan Cameron @ 2025-07-25 12:45 UTC (permalink / raw)
To: shiju.jose
Cc: qemu-devel, linux-cxl, fan.ni, dave, linuxarm, Markus Armbruster,
Eric Blake
On Mon, 21 Jul 2025 18:22:22 +0100
<shiju.jose@huawei.com> wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
> format has updated with optional Maintenance Operation Subclass,
> LD ID and ID of the device head information.
>
> Add updates for the above optional parameters in the related
> CXL events reporting and in the QMP commands to inject CXL events.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
I'll fix up, but this shouldn't have my SoB on the thread.
I'll add that when applying to my staging tree and for sending
this as part of a larger set to Michael.
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
+CC Markus and Eric for the qapi stuff.
I haven't cropped down to bits I've commented on to save them
digging around for the full email.
A few comments inline. Ill carry this updated version on my
gitlab tree with intent to get it upstream early in 10.2 cycle.
Thanks,
Jonathan
> ---
> hw/cxl/cxl-events.c | 3 +-
> hw/cxl/cxl-mailbox-utils.c | 3 +-
> hw/mem/cxl_type3.c | 70 ++++++++++++++++++++++++++++++++-----
> hw/mem/cxl_type3_stubs.c | 24 +++++++++++--
> include/hw/cxl/cxl_device.h | 7 +++-
> include/hw/cxl/cxl_events.h | 15 ++++++--
> qapi/cxl.json | 48 +++++++++++++++++++++++--
> 7 files changed, 150 insertions(+), 20 deletions(-)
>
> diff --git a/hw/cxl/cxl-events.c b/hw/cxl/cxl-events.c
> index 724055f2cf..673154db29 100644
> --- a/hw/cxl/cxl-events.c
> +++ b/hw/cxl/cxl-events.c
> @@ -273,7 +273,8 @@ void cxl_create_dc_event_records_for_extents(CXLType3Dev *ct3d,
> &dynamic_capacity_uuid,
> (1 << CXL_EVENT_TYPE_INFO),
> sizeof(event_rec),
> - cxl_device_get_timestamp(&ct3d->cxl_dstate));
> + cxl_device_get_timestamp(&ct3d->cxl_dstate),
> + 0, 0, 0, 0, 0, 0, 0, 0);
> event_rec.type = type;
> event_rec.validity_flags = 1;
> event_rec.host_id = 0;
> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
> index 43a0d503aa..8f62ea9b54 100644
> --- a/hw/cxl/cxl-mailbox-utils.c
> +++ b/hw/cxl/cxl-mailbox-utils.c
> @@ -3457,7 +3457,8 @@ static CXLRetCode cmd_fm_set_dc_region_config(const struct cxl_cmd *cmd,
> &dynamic_capacity_uuid,
> (1 << CXL_EVENT_TYPE_INFO),
> sizeof(dcEvent),
> - cxl_device_get_timestamp(&ct3d->cxl_dstate));
> + cxl_device_get_timestamp(&ct3d->cxl_dstate),
> + 0, 0, 0, 0, 0, 0, 0, 0);
> dcEvent.type = DC_EVENT_REGION_CONFIG_UPDATED;
> dcEvent.validity_flags = 1;
> dcEvent.host_id = 0;
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index 7676d785c2..aa6e5c1a08 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -1592,12 +1592,39 @@ void qmp_cxl_inject_correctable_error(const char *path, CxlCorErrorType type,
>
> void cxl_assign_event_header(CXLEventRecordHdr *hdr,
> const QemuUUID *uuid, uint32_t flags,
> - uint8_t length, uint64_t timestamp)
> + uint8_t length, uint64_t timestamp,
> + bool has_maint_op_class, uint8_t maint_op_class,
> + bool has_maint_op_subclass,
> + uint8_t maint_op_subclass,
> + bool has_ld_id, uint16_t ld_id,
> + bool has_head_id, uint8_t head_id)
> {
> - st24_le_p(&hdr->flags, flags);
> hdr->length = length;
> memcpy(&hdr->id, uuid, sizeof(hdr->id));
> stq_le_p(&hdr->timestamp, timestamp);
> +
> + if (has_maint_op_class) {
> + hdr->maint_op_class = maint_op_class;
> + } else {
> + hdr->maint_op_class = 0;
> + }
> +
> + if (has_maint_op_subclass) {
> + flags |= CXL_EVENT_REC_FLAGS_MAINT_OP_SUBCLASS_VALID;
> + hdr->maint_op_subclass = maint_op_subclass;
> + }
> +
> + if (has_ld_id) {
> + flags |= CXL_EVENT_REC_FLAGS_LD_ID_VALID;
> + stw_le_p(&hdr->ld_id, ld_id);
> + }
> +
> + if (has_head_id) {
> + flags |= CXL_EVENT_REC_FLAGS_HEAD_ID_VALID;
> + hdr->head_id = head_id;
> + }
> +
> + st24_le_p(&hdr->flags, flags);
> }
>
> static const QemuUUID gen_media_uuid = {
> @@ -1637,7 +1664,13 @@ static int ct3d_qmp_cxl_event_log_enc(CxlEventLog log)
> }
> /* Component ID is device specific. Define this as a string. */
> void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
> - uint8_t flags, uint64_t dpa,
> + uint32_t flags, bool has_maint_op_class,
> + uint8_t maint_op_class,
> + bool has_maint_op_subclass,
> + uint8_t maint_op_subclass,
> + bool has_ld_id, uint16_t ld_id,
> + bool has_head_id, uint8_t head_id,
> + uint64_t dpa,
> uint8_t descriptor, uint8_t type,
> uint8_t transaction_type,
> bool has_channel, uint8_t channel,
> @@ -1675,7 +1708,10 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
>
> memset(&gem, 0, sizeof(gem));
> cxl_assign_event_header(hdr, &gen_media_uuid, flags, sizeof(gem),
> - cxl_device_get_timestamp(&ct3d->cxl_dstate));
> + cxl_device_get_timestamp(&ct3d->cxl_dstate),
> + has_maint_op_class, maint_op_class,
> + has_maint_op_subclass, maint_op_subclass,
> + has_ld_id, ld_id, has_head_id, head_id);
>
> stq_le_p(&gem.phys_addr, dpa);
> gem.descriptor = descriptor;
> @@ -1719,7 +1755,13 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
> #define CXL_DRAM_VALID_COLUMN BIT(6)
> #define CXL_DRAM_VALID_CORRECTION_MASK BIT(7)
>
> -void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
> +void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
> + uint32_t flags,
> + bool has_maint_op_class, uint8_t maint_op_class,
> + bool has_maint_op_subclass,
> + uint8_t maint_op_subclass,
> + bool has_ld_id, uint16_t ld_id,
> + bool has_head_id, uint8_t head_id,
> uint64_t dpa, uint8_t descriptor,
> uint8_t type, uint8_t transaction_type,
> bool has_channel, uint8_t channel,
> @@ -1762,7 +1804,10 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
>
> memset(&dram, 0, sizeof(dram));
> cxl_assign_event_header(hdr, &dram_uuid, flags, sizeof(dram),
> - cxl_device_get_timestamp(&ct3d->cxl_dstate));
> + cxl_device_get_timestamp(&ct3d->cxl_dstate),
> + has_maint_op_class, maint_op_class,
> + has_maint_op_subclass, maint_op_subclass,
> + has_ld_id, ld_id, has_head_id, head_id);
> stq_le_p(&dram.phys_addr, dpa);
> dram.descriptor = descriptor;
> dram.type = type;
> @@ -1822,7 +1867,13 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
> }
>
> void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
> - uint8_t flags, uint8_t type,
> + uint32_t flags, bool has_maint_op_class,
> + uint8_t maint_op_class,
> + bool has_maint_op_subclass,
> + uint8_t maint_op_subclass,
> + bool has_ld_id, uint16_t ld_id,
> + bool has_head_id, uint8_t head_id,
> + uint8_t type,
> uint8_t health_status,
> uint8_t media_status,
> uint8_t additional_status,
> @@ -1861,7 +1912,10 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
>
> memset(&module, 0, sizeof(module));
> cxl_assign_event_header(hdr, &memory_module_uuid, flags, sizeof(module),
> - cxl_device_get_timestamp(&ct3d->cxl_dstate));
> + cxl_device_get_timestamp(&ct3d->cxl_dstate),
> + has_maint_op_class, maint_op_class,
> + has_maint_op_subclass, maint_op_subclass,
> + has_ld_id, ld_id, has_head_id, head_id);
>
> module.type = type;
> module.health_status = health_status;
> diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
> index c1a5e4a7c1..91b1478114 100644
> --- a/hw/mem/cxl_type3_stubs.c
> +++ b/hw/mem/cxl_type3_stubs.c
> @@ -14,7 +14,13 @@
> #include "qapi/qapi-commands-cxl.h"
>
> void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
> - uint8_t flags, uint64_t dpa,
> + uint32_t flags, bool has_maint_op_class,
> + uint8_t maint_op_class,
> + bool has_maint_op_subclass,
> + uint8_t maint_op_subclass,
> + bool has_ld_id, uint16_t ld_id,
> + bool has_head_id, uint8_t head_id,
> + uint64_t dpa,
> uint8_t descriptor, uint8_t type,
> uint8_t transaction_type,
> bool has_channel, uint8_t channel,
> @@ -23,7 +29,13 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
> const char *component_id,
> Error **errp) {}
>
> -void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
> +void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
> + uint32_t flags,
> + bool has_maint_op_class, uint8_t maint_op_class,
> + bool has_maint_op_subclass,
> + uint8_t maint_op_subclass,
> + bool has_ld_id, uint16_t ld_id,
> + bool has_head_id, uint8_t head_id,
> uint64_t dpa, uint8_t descriptor,
> uint8_t type, uint8_t transaction_type,
> bool has_channel, uint8_t channel,
> @@ -38,7 +50,13 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
> Error **errp) {}
>
> void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
> - uint8_t flags, uint8_t type,
> + uint32_t flags, bool has_maint_op_class,
> + uint8_t maint_op_class,
> + bool has_maint_op_subclass,
> + uint8_t maint_op_subclass,
> + bool has_ld_id, uint16_t ld_id,
> + bool has_head_id, uint8_t head_id,
> + uint8_t type,
> uint8_t health_status,
> uint8_t media_status,
> uint8_t additional_status,
> diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> index fdee60b977..b77b6b2499 100644
> --- a/include/hw/cxl/cxl_device.h
> +++ b/include/hw/cxl/cxl_device.h
> @@ -723,7 +723,12 @@ bool ct3_test_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,
> uint64_t len);
> void cxl_assign_event_header(CXLEventRecordHdr *hdr,
> const QemuUUID *uuid, uint32_t flags,
> - uint8_t length, uint64_t timestamp);
> + uint8_t length, uint64_t timestamp,
> + bool has_maint_op_class, uint8_t maint_op_class,
> + bool has_maint_op_subclass,
> + uint8_t maint_op_subclass,
> + bool has_ld_id, uint16_t ld_id,
> + bool has_head_id, uint8_t head_id);
> void cxl_create_dc_event_records_for_extents(CXLType3Dev *ct3d,
> CXLDCEventType type,
> CXLDCExtentRaw extents[],
> diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
> index 758b075a64..4d9cfdb621 100644
> --- a/include/hw/cxl/cxl_events.h
> +++ b/include/hw/cxl/cxl_events.h
> @@ -29,9 +29,15 @@ typedef enum CXLEventLogType {
>
> /*
> * Common Event Record Format
> - * CXL r3.1 section 8.2.9.2.1: Event Records; Table 8-43
> + * CXL r3.2 section 8.2.10.2.1: Event Records; Table 8-55
> */
> -#define CXL_EVENT_REC_HDR_RES_LEN 0xf
> +#define CXL_EVENT_REC_FLAGS_PERMANENT_COND BIT(2)
> +#define CXL_EVENT_REC_FLAGS_MAINT_NEEDED BIT(3)
> +#define CXL_EVENT_REC_FLAGS_PERF_DEGRADED BIT(4)
> +#define CXL_EVENT_REC_FLAGS_HW_REPLACEMENT_NEEDED BIT(5)
> +#define CXL_EVENT_REC_FLAGS_MAINT_OP_SUBCLASS_VALID BIT(6)
> +#define CXL_EVENT_REC_FLAGS_LD_ID_VALID BIT(7)
> +#define CXL_EVENT_REC_FLAGS_HEAD_ID_VALID BIT(8)
> typedef struct CXLEventRecordHdr {
> QemuUUID id;
> uint8_t length;
> @@ -40,7 +46,10 @@ typedef struct CXLEventRecordHdr {
> uint16_t related_handle;
> uint64_t timestamp;
> uint8_t maint_op_class;
> - uint8_t reserved[CXL_EVENT_REC_HDR_RES_LEN];
> + uint8_t maint_op_subclass;
> + uint16_t ld_id;
> + uint8_t head_id;
> + uint8_t reserved[0xb];
> } QEMU_PACKED CXLEventRecordHdr;
>
> #define CXL_EVENT_RECORD_DATA_LENGTH 0x50
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index 8f2e9237b1..c1fe8319c8 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -42,6 +42,18 @@
> # @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
> # Record Format, Event Record Flags for subfield definitions.
> #
> +# @maint-op-class: Maintenance operation class the device requests to initiate.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @maint-op-subclass: Maintenance operation subclass the device requests to
> +# initiate. See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @ld-id: LD ID of LD from where the event originated.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @head-id: ID of the device head from where the event originated.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> # @dpa: Device Physical Address (relative to @path device). Note
> # lower bits include some flags. See CXL r3.0 Table 8-43 General
> # Media Event Record, Physical Address.
> @@ -73,7 +85,9 @@
> # Since: 8.1
> ##
> { 'command': 'cxl-inject-general-media-event',
> - 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
> + 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint32',
> + '*maint-op-class':'uint8', '*maint-op-subclass':'uint8',
> + '*ld-id':'uint16', '*head-id':'uint8',
> 'dpa': 'uint64', 'descriptor': 'uint8',
> 'type': 'uint8', 'transaction-type': 'uint8',
> '*channel': 'uint8', '*rank': 'uint8',
> @@ -93,6 +107,18 @@
> # @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
> # Record Format, Event Record Flags for subfield definitions.
> #
> +# @maint-op-class: Maintenance operation class the device requests to initiate.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @maint-op-subclass: Maintenance operation subclass the device requests to
> +# initiate. See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @ld-id: LD ID of LD from where the event originated.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @head-id: ID of the device head from where the event originated.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> # @dpa: Device Physical Address (relative to @path device). Note
> # lower bits include some flags. See CXL r3.0 Table 8-44 DRAM
> # Event Record, Physical Address.
> @@ -132,7 +158,9 @@
> # Since: 8.1
> ##
> { 'command': 'cxl-inject-dram-event',
> - 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
> + 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint32',
> + '*maint-op-class':'uint8', '*maint-op-subclass':'uint8',
> + '*ld-id':'uint16', '*head-id':'uint8',
Some tabs in here. I'll fix up.
> 'dpa': 'uint64', 'descriptor': 'uint8',
> 'type': 'uint8', 'transaction-type': 'uint8',
> '*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
> @@ -154,6 +182,18 @@
> # @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
> # Record Format, Event Record Flags for subfield definitions.
> #
> +# @maint-op-class: Maintenance operation class the device requests to initiate.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @maint-op-subclass: Maintenance operation subclass the device requests to
> +# initiate. See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @ld-id: LD ID of LD from where the event originated.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @head-id: ID of the device head from where the event originated.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> # @type: Device Event Type. See CXL r3.0 Table 8-45 Memory Module
> # Event Record for bit definitions for bit definiions.
> #
> @@ -184,7 +224,9 @@
> # Since: 8.1
> ##
> { 'command': 'cxl-inject-memory-module-event',
> - 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags' : 'uint8',
> + 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags' : 'uint32',
> + '*maint-op-class':'uint8', '*maint-op-subclass':'uint8',
> + '*ld-id':'uint16', '*head-id':'uint8',
Here as well.
> 'type': 'uint8', 'health-status': 'uint8',
> 'media-status': 'uint8', 'additional-status': 'uint8',
> 'life-used': 'uint8', 'temperature' : 'int16',
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH qemu v4 1/7] hw/cxl/events: Update for rev3.2 common event record format
2025-07-21 17:22 ` [PATCH qemu v4 1/7] hw/cxl/events: Update for rev3.2 common event record format shiju.jose
2025-07-25 12:45 ` Jonathan Cameron
@ 2025-08-06 7:45 ` Markus Armbruster
1 sibling, 0 replies; 17+ messages in thread
From: Markus Armbruster @ 2025-08-06 7:45 UTC (permalink / raw)
To: shiju.jose--- via
Cc: linux-cxl, jonathan.cameron, fan.ni, dave, shiju.jose, linuxarm
shiju.jose--- via <qemu-devel@nongnu.org> writes:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
> format has updated with optional Maintenance Operation Subclass,
> LD ID and ID of the device head information.
>
> Add updates for the above optional parameters in the related
> CXL events reporting and in the QMP commands to inject CXL events.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
[...]
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index 8f2e9237b1..c1fe8319c8 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -42,6 +42,18 @@
> # @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
> # Record Format, Event Record Flags for subfield definitions.
> #
> +# @maint-op-class: Maintenance operation class the device requests to initiate.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @maint-op-subclass: Maintenance operation subclass the device requests to
> +# initiate. See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @ld-id: LD ID of LD from where the event originated.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @head-id: ID of the device head from where the event originated.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> # @dpa: Device Physical Address (relative to @path device). Note
> # lower bits include some flags. See CXL r3.0 Table 8-43 General
> # Media Event Record, Physical Address.
From docs/devel/qapi-code-gen.rst:
For legibility, wrap text paragraphs so every line is at most 70
characters long.
Separate sentences with two spaces.
> @@ -73,7 +85,9 @@
> # Since: 8.1
> ##
> { 'command': 'cxl-inject-general-media-event',
> - 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
> + 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint32',
> + '*maint-op-class':'uint8', '*maint-op-subclass':'uint8',
> + '*ld-id':'uint16', '*head-id':'uint8',
> 'dpa': 'uint64', 'descriptor': 'uint8',
> 'type': 'uint8', 'transaction-type': 'uint8',
> '*channel': 'uint8', '*rank': 'uint8',
> @@ -93,6 +107,18 @@
> # @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
> # Record Format, Event Record Flags for subfield definitions.
> #
> +# @maint-op-class: Maintenance operation class the device requests to initiate.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @maint-op-subclass: Maintenance operation subclass the device requests to
> +# initiate. See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @ld-id: LD ID of LD from where the event originated.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @head-id: ID of the device head from where the event originated.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> # @dpa: Device Physical Address (relative to @path device). Note
> # lower bits include some flags. See CXL r3.0 Table 8-44 DRAM
> # Event Record, Physical Address.
> @@ -132,7 +158,9 @@
> # Since: 8.1
> ##
> { 'command': 'cxl-inject-dram-event',
> - 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
> + 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint32',
> + '*maint-op-class':'uint8', '*maint-op-subclass':'uint8',
> + '*ld-id':'uint16', '*head-id':'uint8',
> 'dpa': 'uint64', 'descriptor': 'uint8',
> 'type': 'uint8', 'transaction-type': 'uint8',
> '*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
> @@ -154,6 +182,18 @@
> # @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event
> # Record Format, Event Record Flags for subfield definitions.
> #
> +# @maint-op-class: Maintenance operation class the device requests to initiate.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @maint-op-subclass: Maintenance operation subclass the device requests to
> +# initiate. See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @ld-id: LD ID of LD from where the event originated.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> +# @head-id: ID of the device head from where the event originated.
> +# See CXL r3.2 Table 8-55 Common Event Record Format.
> +#
> # @type: Device Event Type. See CXL r3.0 Table 8-45 Memory Module
> # Event Record for bit definitions for bit definiions.
> #
> @@ -184,7 +224,9 @@
> # Since: 8.1
> ##
> { 'command': 'cxl-inject-memory-module-event',
> - 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags' : 'uint8',
> + 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags' : 'uint32',
> + '*maint-op-class':'uint8', '*maint-op-subclass':'uint8',
> + '*ld-id':'uint16', '*head-id':'uint8',
> 'type': 'uint8', 'health-status': 'uint8',
> 'media-status': 'uint8', 'additional-status': 'uint8',
> 'life-used': 'uint8', 'temperature' : 'int16',
This adds identical copies to three commands.
You can factor out common command arguments as follows.
1. Switch commands from implicit to explicit argument type.
{ 'command': 'cmd1', 'data': { ARGS1... } ... }
becomes
{ 'struct': 'Args1', 'data': { ARGS1... } }
{ 'command': 'cmd1', 'data': 'Args1' ... }
2. Factor common base out of the argument types.
{ 'struct': 'Args1', 'data': { COMMON-ARGS..., SPECIAL-ARGS1... } }
becomes
{ 'struct': 'Base, 'data': { COMMON-ARGS... } }
{ 'struct': 'Args1', 'base': 'Base', 'data': { SPECIAL-ARGS1... } }
3. Maybe use 'boxed': true with commands.
The C function generated for a command with many arguments can be
rather unwieldy. 'boxed': true makes it take the arguments as a
single struct type instead.
This is not a demand. Just give it a thought.
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH qemu v4 2/7] hw/cxl/events: Updates for rev3.2 general media event record
2025-07-21 17:22 [PATCH qemu v4 0/7] hw/cxl: Update CXL events to rev3.2 and add maintenance support for memory repair features shiju.jose
2025-07-21 17:22 ` [PATCH qemu v4 1/7] hw/cxl/events: Update for rev3.2 common event record format shiju.jose
@ 2025-07-21 17:22 ` shiju.jose
2025-08-06 7:57 ` Markus Armbruster
2025-07-21 17:22 ` [PATCH qemu v4 3/7] hw/cxl/events: Updates for rev3.2 DRAM " shiju.jose
` (4 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: shiju.jose @ 2025-07-21 17:22 UTC (permalink / raw)
To: qemu-devel, linux-cxl, jonathan.cameron, fan.ni, dave
Cc: linuxarm, shiju.jose
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event
table has updated with following new fields.
1. Advanced Programmable Corrected Memory Error Threshold Event Flags
2. Corrected Memory Error Count at Event
3. Memory Event Sub-Type
4. Support for component ID in the PLDM format.
Add updates for the above spec changes in the CXL general media event
reporting and QMP command to inject general media event.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
hw/mem/cxl_type3.c | 29 +++++++++++++++++++++++++++++
hw/mem/cxl_type3_stubs.c | 6 ++++++
include/hw/cxl/cxl_events.h | 7 +++++--
qapi/cxl.json | 18 +++++++++++++++++-
4 files changed, 57 insertions(+), 3 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index aa6e5c1a08..a10e6bf518 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1646,6 +1646,11 @@ static const QemuUUID memory_module_uuid = {
#define CXL_GMER_VALID_RANK BIT(1)
#define CXL_GMER_VALID_DEVICE BIT(2)
#define CXL_GMER_VALID_COMPONENT BIT(3)
+#define CXL_GMER_VALID_COMPONENT_ID_FORMAT BIT(4)
+
+#define CXL_GMER_EV_DESC_UCE BIT(0)
+#define CXL_GMER_EV_DESC_THRESHOLD_EVENT BIT(1)
+#define CXL_GMER_EV_DESC_POISON_LIST_OVERFLOW_EVENT BIT(2)
static int ct3d_qmp_cxl_event_log_enc(CxlEventLog log)
{
@@ -1677,6 +1682,12 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
bool has_rank, uint8_t rank,
bool has_device, uint32_t device,
const char *component_id,
+ bool has_comp_id_pldm,
+ uint8_t is_comp_id_pldm,
+ bool has_cme_ev_flags,
+ uint8_t cme_ev_flags,
+ bool has_cme_count, uint32_t cme_count,
+ uint8_t sub_type,
Error **errp)
{
Object *obj = object_resolve_path(path, NULL);
@@ -1737,10 +1748,28 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
strncpy((char *)gem.component_id, component_id,
sizeof(gem.component_id) - 1);
valid_flags |= CXL_GMER_VALID_COMPONENT;
+ if (has_comp_id_pldm && is_comp_id_pldm) {
+ valid_flags |= CXL_GMER_VALID_COMPONENT_ID_FORMAT;
+ }
}
stw_le_p(&gem.validity_flags, valid_flags);
+ if (has_cme_ev_flags) {
+ gem.cme_ev_flags = cme_ev_flags;
+ } else {
+ gem.cme_ev_flags = 0;
+ }
+
+ if (has_cme_count) {
+ descriptor |= CXL_GMER_EV_DESC_THRESHOLD_EVENT;
+ st24_le_p(gem.cme_count, cme_count);
+ } else {
+ st24_le_p(gem.cme_count, 0);
+ }
+
+ gem.sub_type = sub_type;
+
if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&gem)) {
cxl_event_irq_assert(ct3d);
}
diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
index 91b1478114..28eb880b30 100644
--- a/hw/mem/cxl_type3_stubs.c
+++ b/hw/mem/cxl_type3_stubs.c
@@ -27,6 +27,12 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
bool has_rank, uint8_t rank,
bool has_device, uint32_t device,
const char *component_id,
+ bool has_comp_id_pldm,
+ uint8_t is_comp_id_pldm,
+ bool has_cme_ev_flags,
+ uint8_t cme_ev_flags,
+ bool has_cme_count, uint32_t cme_count,
+ uint8_t sub_type,
Error **errp) {}
void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
index 4d9cfdb621..352f9891bd 100644
--- a/include/hw/cxl/cxl_events.h
+++ b/include/hw/cxl/cxl_events.h
@@ -115,10 +115,10 @@ typedef struct CXLEventInterruptPolicy {
/*
* General Media Event Record
- * CXL r3.1 Section 8.2.9.2.1.1; Table 8-45
+ * CXL r3.2 Section 8.2.10.2.1.1; Table 8-57
*/
#define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
-#define CXL_EVENT_GEN_MED_RES_SIZE 0x2e
+#define CXL_EVENT_GEN_MED_RES_SIZE 0x29
typedef struct CXLEventGenMedia {
CXLEventRecordHdr hdr;
uint64_t phys_addr;
@@ -130,6 +130,9 @@ typedef struct CXLEventGenMedia {
uint8_t rank;
uint8_t device[3];
uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
+ uint8_t cme_ev_flags;
+ uint8_t cme_count[3];
+ uint8_t sub_type;
uint8_t reserved[CXL_EVENT_GEN_MED_RES_SIZE];
} QEMU_PACKED CXLEventGenMedia;
diff --git a/qapi/cxl.json b/qapi/cxl.json
index c1fe8319c8..e8060d16f7 100644
--- a/qapi/cxl.json
+++ b/qapi/cxl.json
@@ -82,6 +82,19 @@
# @component-id: Device specific component identifier for the event.
# May describe a field replaceable sub-component of the device.
#
+# @is-comp-id-pldm: Flag represents device specific component identifier
+# format is PLDM or not.
+#
+# @cme-ev-flags: Advanced programmable corrected memory error
+# threshold event flags.
+# See CXL r3.2 Table 8-57 General Media Event Record.
+#
+# @cme-count: Corrected memory error count at event.
+# See CXL r3.2 Table 8-57 General Media Event Record.
+#
+# @sub-type: Memory event sub-type.
+# See CXL r3.2 Table 8-57 General Media Event Record.
+#
# Since: 8.1
##
{ 'command': 'cxl-inject-general-media-event',
@@ -91,7 +104,10 @@
'dpa': 'uint64', 'descriptor': 'uint8',
'type': 'uint8', 'transaction-type': 'uint8',
'*channel': 'uint8', '*rank': 'uint8',
- '*device': 'uint32', '*component-id': 'str' } }
+ '*device': 'uint32', '*component-id': 'str',
+ '*is-comp-id-pldm':'uint8',
+ '*cme-ev-flags':'uint8', '*cme-count':'uint32',
+ 'sub-type':'uint8' } }
##
# @cxl-inject-dram-event:
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH qemu v4 2/7] hw/cxl/events: Updates for rev3.2 general media event record
2025-07-21 17:22 ` [PATCH qemu v4 2/7] hw/cxl/events: Updates for rev3.2 general media event record shiju.jose
@ 2025-08-06 7:57 ` Markus Armbruster
2025-08-06 9:21 ` Shiju Jose
0 siblings, 1 reply; 17+ messages in thread
From: Markus Armbruster @ 2025-08-06 7:57 UTC (permalink / raw)
To: shiju.jose--- via
Cc: linux-cxl, jonathan.cameron, fan.ni, dave, shiju.jose, linuxarm
shiju.jose--- via <qemu-devel@nongnu.org> writes:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event
> table has updated with following new fields.
> 1. Advanced Programmable Corrected Memory Error Threshold Event Flags
> 2. Corrected Memory Error Count at Event
> 3. Memory Event Sub-Type
> 4. Support for component ID in the PLDM format.
>
> Add updates for the above spec changes in the CXL general media event
> reporting and QMP command to inject general media event.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
[...]
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index c1fe8319c8..e8060d16f7 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -82,6 +82,19 @@
> # @component-id: Device specific component identifier for the event.
> # May describe a field replaceable sub-component of the device.
> #
> +# @is-comp-id-pldm: Flag represents device specific component identifier
> +# format is PLDM or not.
Awkward phrasing. Before I can suggest a better one, I have a question.
The type is uint8, which isn't a flag. What are the possible values?
> +#
> +# @cme-ev-flags: Advanced programmable corrected memory error
> +# threshold event flags.
> +# See CXL r3.2 Table 8-57 General Media Event Record.
The line break will not make it into generated HTML (it's all one
wrapped paragraph).
We commonly wrap like this:
# @cme-ev-flags: Advanced programmable corrected memory error
# threshold event flags. See CXL r3.2 Table 8-57 General Media
# Event Record.
If you want a line break in generated documentation, you need to start a
new paragraph like this:
# @cme-ev-flags: Advanced programmable corrected memory error
# threshold event flags.
#
# See CXL r3.2 Table 8-57 General Media Event Record.
Same below.
> +#
> +# @cme-count: Corrected memory error count at event.
> +# See CXL r3.2 Table 8-57 General Media Event Record.
> +#
> +# @sub-type: Memory event sub-type.
> +# See CXL r3.2 Table 8-57 General Media Event Record.
> +#
> # Since: 8.1
> ##
> { 'command': 'cxl-inject-general-media-event',
> @@ -91,7 +104,10 @@
> 'dpa': 'uint64', 'descriptor': 'uint8',
> 'type': 'uint8', 'transaction-type': 'uint8',
> '*channel': 'uint8', '*rank': 'uint8',
> - '*device': 'uint32', '*component-id': 'str' } }
> + '*device': 'uint32', '*component-id': 'str',
> + '*is-comp-id-pldm':'uint8',
> + '*cme-ev-flags':'uint8', '*cme-count':'uint32',
> + 'sub-type':'uint8' } }
>
> ##
> # @cxl-inject-dram-event:
^ permalink raw reply [flat|nested] 17+ messages in thread* RE: [PATCH qemu v4 2/7] hw/cxl/events: Updates for rev3.2 general media event record
2025-08-06 7:57 ` Markus Armbruster
@ 2025-08-06 9:21 ` Shiju Jose
2025-08-06 10:23 ` Markus Armbruster
0 siblings, 1 reply; 17+ messages in thread
From: Shiju Jose @ 2025-08-06 9:21 UTC (permalink / raw)
To: Markus Armbruster, shiju.jose--- via
Cc: linux-cxl@vger.kernel.org, Jonathan Cameron, fan.ni@samsung.com,
dave@stgolabs.net, Linuxarm
>-----Original Message-----
>From: Markus Armbruster <armbru@redhat.com>
>Sent: 06 August 2025 08:58
>To: shiju.jose--- via <qemu-devel@nongnu.org>
>Cc: linux-cxl@vger.kernel.org; Jonathan Cameron
><jonathan.cameron@huawei.com>; fan.ni@samsung.com; dave@stgolabs.net;
>Shiju Jose <shiju.jose@huawei.com>; Linuxarm <linuxarm@huawei.com>
>Subject: Re: [PATCH qemu v4 2/7] hw/cxl/events: Updates for rev3.2 general
>media event record
>
>shiju.jose--- via <qemu-devel@nongnu.org> writes:
>
>> From: Shiju Jose <shiju.jose@huawei.com>
>>
>> CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event
>> table has updated with following new fields.
>> 1. Advanced Programmable Corrected Memory Error Threshold Event Flags
>> 2. Corrected Memory Error Count at Event 3. Memory Event Sub-Type 4.
>> Support for component ID in the PLDM format.
>>
>> Add updates for the above spec changes in the CXL general media event
>> reporting and QMP command to inject general media event.
>>
>> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
>
>[...]
>
>> diff --git a/qapi/cxl.json b/qapi/cxl.json index
>> c1fe8319c8..e8060d16f7 100644
>> --- a/qapi/cxl.json
>> +++ b/qapi/cxl.json
>> @@ -82,6 +82,19 @@
>> # @component-id: Device specific component identifier for the event.
>> # May describe a field replaceable sub-component of the device.
>> #
>> +# @is-comp-id-pldm: Flag represents device specific component identifier
>> +# format is PLDM or not.
>
>Awkward phrasing. Before I can suggest a better one, I have a question.
>The type is uint8, which isn't a flag. What are the possible values?
Thanks Markus for the comments.
'is-comp-id-pldm' is flag with possible values 0 and 1.
I will use type bool instead of uint8?
>
>> +#
>> +# @cme-ev-flags: Advanced programmable corrected memory error
>> +# threshold event flags.
>> +# See CXL r3.2 Table 8-57 General Media Event Record.
>
>The line break will not make it into generated HTML (it's all one wrapped
>paragraph).
>
>We commonly wrap like this:
Will fix.
>
> # @cme-ev-flags: Advanced programmable corrected memory error
> # threshold event flags. See CXL r3.2 Table 8-57 General Media
> # Event Record.
>
>If you want a line break in generated documentation, you need to start a new
>paragraph like this:
>
> # @cme-ev-flags: Advanced programmable corrected memory error
> # threshold event flags.
> #
> # See CXL r3.2 Table 8-57 General Media Event Record.
>
>Same below.
Will fix.
>
>> +#
>> +# @cme-count: Corrected memory error count at event.
>> +# See CXL r3.2 Table 8-57 General Media Event Record.
>> +#
>> +# @sub-type: Memory event sub-type.
>> +# See CXL r3.2 Table 8-57 General Media Event Record.
>> +#
>> # Since: 8.1
>> ##
>> { 'command': 'cxl-inject-general-media-event', @@ -91,7 +104,10 @@
>> 'dpa': 'uint64', 'descriptor': 'uint8',
>> 'type': 'uint8', 'transaction-type': 'uint8',
>> '*channel': 'uint8', '*rank': 'uint8',
>> - '*device': 'uint32', '*component-id': 'str' } }
>> + '*device': 'uint32', '*component-id': 'str',
>> + '*is-comp-id-pldm':'uint8',
>> + '*cme-ev-flags':'uint8', '*cme-count':'uint32',
>> + 'sub-type':'uint8' } }
>>
>> ##
>> # @cxl-inject-dram-event:
>
Thanks,
Shiju
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH qemu v4 2/7] hw/cxl/events: Updates for rev3.2 general media event record
2025-08-06 9:21 ` Shiju Jose
@ 2025-08-06 10:23 ` Markus Armbruster
0 siblings, 0 replies; 17+ messages in thread
From: Markus Armbruster @ 2025-08-06 10:23 UTC (permalink / raw)
To: Shiju Jose
Cc: shiju.jose--- via, linux-cxl@vger.kernel.org, Jonathan Cameron,
fan.ni@samsung.com, dave@stgolabs.net, Linuxarm
Shiju Jose <shiju.jose@huawei.com> writes:
>>-----Original Message-----
>>From: Markus Armbruster <armbru@redhat.com>
>>Sent: 06 August 2025 08:58
>>To: shiju.jose--- via <qemu-devel@nongnu.org>
>>Cc: linux-cxl@vger.kernel.org; Jonathan Cameron
>><jonathan.cameron@huawei.com>; fan.ni@samsung.com; dave@stgolabs.net;
>>Shiju Jose <shiju.jose@huawei.com>; Linuxarm <linuxarm@huawei.com>
>>Subject: Re: [PATCH qemu v4 2/7] hw/cxl/events: Updates for rev3.2 general
>>media event record
>>
>>shiju.jose--- via <qemu-devel@nongnu.org> writes:
>>
>>> From: Shiju Jose <shiju.jose@huawei.com>
>>>
>>> CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event
>>> table has updated with following new fields.
>>> 1. Advanced Programmable Corrected Memory Error Threshold Event Flags
>>> 2. Corrected Memory Error Count at Event 3. Memory Event Sub-Type 4.
>>> Support for component ID in the PLDM format.
>>>
>>> Add updates for the above spec changes in the CXL general media event
>>> reporting and QMP command to inject general media event.
>>>
>>> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>>> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
>>
>>[...]
>>
>>> diff --git a/qapi/cxl.json b/qapi/cxl.json index
>>> c1fe8319c8..e8060d16f7 100644
>>> --- a/qapi/cxl.json
>>> +++ b/qapi/cxl.json
>>> @@ -82,6 +82,19 @@
>>> # @component-id: Device specific component identifier for the event.
>>> # May describe a field replaceable sub-component of the device.
>>> #
>>> +# @is-comp-id-pldm: Flag represents device specific component identifier
>>> +# format is PLDM or not.
>>
>>Awkward phrasing. Before I can suggest a better one, I have a question.
>>The type is uint8, which isn't a flag. What are the possible values?
> Thanks Markus for the comments.
You're welcome!
> 'is-comp-id-pldm' is flag with possible values 0 and 1.
> I will use type bool instead of uint8?
Yes, please!
[...]
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH qemu v4 3/7] hw/cxl/events: Updates for rev3.2 DRAM event record
2025-07-21 17:22 [PATCH qemu v4 0/7] hw/cxl: Update CXL events to rev3.2 and add maintenance support for memory repair features shiju.jose
2025-07-21 17:22 ` [PATCH qemu v4 1/7] hw/cxl/events: Update for rev3.2 common event record format shiju.jose
2025-07-21 17:22 ` [PATCH qemu v4 2/7] hw/cxl/events: Updates for rev3.2 general media event record shiju.jose
@ 2025-07-21 17:22 ` shiju.jose
2025-08-06 8:05 ` Markus Armbruster
2025-07-21 17:22 ` [PATCH qemu v4 4/7] hw/cxl/events: Updates for rev3.2 memory module " shiju.jose
` (3 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: shiju.jose @ 2025-07-21 17:22 UTC (permalink / raw)
To: qemu-devel, linux-cxl, jonathan.cameron, fan.ni, dave
Cc: linuxarm, shiju.jose
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec rev3.2 section 8.2.10.2.1.2 Table 8-58, DRAM event record
has updated with following new fields.
1. Component Identifier
2. Sub-channel of the memory event location
3. Advanced Programmable Corrected Memory Error Threshold Event Flags
4. Corrected Volatile Memory Error Count at Event
5. Memory Event Sub-Type
Add updates for the above spec changes in the CXL DRAM event
reporting and QMP command to inject DRAM event.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
hw/mem/cxl_type3.c | 42 +++++++++++++++++++++++++++++++++++++
hw/mem/cxl_type3_stubs.c | 7 +++++++
include/hw/cxl/cxl_events.h | 9 ++++++--
qapi/cxl.json | 26 ++++++++++++++++++++++-
4 files changed, 81 insertions(+), 3 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index a10e6bf518..afe5ceb1c9 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1783,6 +1783,13 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
#define CXL_DRAM_VALID_ROW BIT(5)
#define CXL_DRAM_VALID_COLUMN BIT(6)
#define CXL_DRAM_VALID_CORRECTION_MASK BIT(7)
+#define CXL_DRAM_VALID_COMPONENT BIT(8)
+#define CXL_DRAM_VALID_COMPONENT_ID_FORMAT BIT(9)
+#define CXL_DRAM_VALID_SUB_CHANNEL BIT(10)
+
+#define CXL_DRAM_EV_DESC_UCE BIT(0)
+#define CXL_DRAM_EV_DESC_THRESHOLD_EVENT BIT(1)
+#define CXL_DRAM_EV_DESC_POISON_LIST_OVERFLOW_EVENT BIT(2)
void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
uint32_t flags,
@@ -1802,6 +1809,12 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
bool has_column, uint16_t column,
bool has_correction_mask,
uint64List *correction_mask,
+ const char *component_id,
+ bool has_comp_id_pldm, uint8_t is_comp_id_pldm,
+ bool has_sub_channel, uint8_t sub_channel,
+ bool has_cme_ev_flags, uint8_t cme_ev_flags,
+ bool has_cvme_count, uint32_t cvme_count,
+ uint8_t sub_type,
Error **errp)
{
Object *obj = object_resolve_path(path, NULL);
@@ -1888,6 +1901,35 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
valid_flags |= CXL_DRAM_VALID_CORRECTION_MASK;
}
+ if (component_id) {
+ strncpy((char *)dram.component_id, component_id,
+ sizeof(dram.component_id) - 1);
+ valid_flags |= CXL_DRAM_VALID_COMPONENT;
+ if (has_comp_id_pldm && is_comp_id_pldm) {
+ valid_flags |= CXL_DRAM_VALID_COMPONENT_ID_FORMAT;
+ }
+ }
+
+ if (has_sub_channel) {
+ dram.sub_channel = sub_channel;
+ valid_flags |= CXL_DRAM_VALID_SUB_CHANNEL;
+ }
+
+ if (has_cme_ev_flags) {
+ dram.cme_ev_flags = cme_ev_flags;
+ } else {
+ dram.cme_ev_flags = 0;
+ }
+
+ if (has_cvme_count) {
+ descriptor |= CXL_DRAM_EV_DESC_THRESHOLD_EVENT;
+ st24_le_p(dram.cvme_count, cvme_count);
+ } else {
+ st24_le_p(dram.cvme_count, 0);
+ }
+
+ dram.sub_type = sub_type;
+
stw_le_p(&dram.validity_flags, valid_flags);
if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&dram)) {
diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
index 28eb880b30..c3cd97b5b7 100644
--- a/hw/mem/cxl_type3_stubs.c
+++ b/hw/mem/cxl_type3_stubs.c
@@ -53,6 +53,13 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
bool has_column, uint16_t column,
bool has_correction_mask,
uint64List *correction_mask,
+ const char *component_id,
+ bool has_comp_id_pldm,
+ uint8_t is_comp_id_pldm,
+ bool has_sub_channel, uint8_t sub_channel,
+ bool has_cme_ev_flags, uint8_t cme_ev_flags,
+ bool has_cvme_count, uint32_t cvme_count,
+ uint8_t sub_type,
Error **errp) {}
void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
index 352f9891bd..a3c5f2ec20 100644
--- a/include/hw/cxl/cxl_events.h
+++ b/include/hw/cxl/cxl_events.h
@@ -138,7 +138,7 @@ typedef struct CXLEventGenMedia {
/*
* DRAM Event Record
- * CXL r3.1 Section 8.2.9.2.1.2: Table 8-46
+ * CXL r3.2 Section 8.2.10.2.1.2: Table 8-58
* All fields little endian.
*/
typedef struct CXLEventDram {
@@ -156,7 +156,12 @@ typedef struct CXLEventDram {
uint8_t row[3];
uint16_t column;
uint64_t correction_mask[4];
- uint8_t reserved[0x17];
+ uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
+ uint8_t sub_channel;
+ uint8_t cme_ev_flags;
+ uint8_t cvme_count[3];
+ uint8_t sub_type;
+ uint8_t reserved;
} QEMU_PACKED CXLEventDram;
/*
diff --git a/qapi/cxl.json b/qapi/cxl.json
index e8060d16f7..f84088c0b9 100644
--- a/qapi/cxl.json
+++ b/qapi/cxl.json
@@ -171,6 +171,26 @@
# @correction-mask: Bits within each nibble. Used in order of bits
# set in the nibble-mask. Up to 4 nibbles may be covered.
#
+# @component-id: Device specific component identifier for the event.
+# May describe a field replaceable sub-component of the device.
+# See CXL r3.2 Table 8-58 DRAM Event Record.
+#
+# @is-comp-id-pldm: Flag represents device specific component identifier
+# format is PLDM or not.
+#
+# @sub-channel: The sub-channel of the memory event location.
+# See CXL r3.2 Table 8-58 DRAM Event Record.
+#
+# @cme-ev-flags: Advanced programmable corrected memory error
+# threshold event flags.
+# See CXL r3.2 Table 8-58 DRAM Event Record.
+#
+# @cvme-count: Corrected volatile memory error count at event.
+# See CXL r3.2 Table 8-58 DRAM Event Record.
+#
+# @sub-type: Memory event sub-type.
+# See CXL r3.2 Table 8-58 DRAM Event Record.
+#
# Since: 8.1
##
{ 'command': 'cxl-inject-dram-event',
@@ -181,7 +201,11 @@
'type': 'uint8', 'transaction-type': 'uint8',
'*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
'*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
- '*column': 'uint16', '*correction-mask': [ 'uint64' ]
+ '*column': 'uint16', '*correction-mask': [ 'uint64' ],
+ '*component-id': 'str', '*is-comp-id-pldm':'uint8',
+ '*sub-channel':'uint8',
+ '*cme-ev-flags':'uint8', '*cvme-count':'uint32',
+ 'sub-type':'uint8'
}}
##
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH qemu v4 3/7] hw/cxl/events: Updates for rev3.2 DRAM event record
2025-07-21 17:22 ` [PATCH qemu v4 3/7] hw/cxl/events: Updates for rev3.2 DRAM " shiju.jose
@ 2025-08-06 8:05 ` Markus Armbruster
0 siblings, 0 replies; 17+ messages in thread
From: Markus Armbruster @ 2025-08-06 8:05 UTC (permalink / raw)
To: shiju.jose--- via
Cc: linux-cxl, jonathan.cameron, fan.ni, dave, shiju.jose, linuxarm
shiju.jose--- via <qemu-devel@nongnu.org> writes:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec rev3.2 section 8.2.10.2.1.2 Table 8-58, DRAM event record
> has updated with following new fields.
> 1. Component Identifier
> 2. Sub-channel of the memory event location
> 3. Advanced Programmable Corrected Memory Error Threshold Event Flags
> 4. Corrected Volatile Memory Error Count at Event
> 5. Memory Event Sub-Type
>
> Add updates for the above spec changes in the CXL DRAM event
> reporting and QMP command to inject DRAM event.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
[...]
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index e8060d16f7..f84088c0b9 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -171,6 +171,26 @@
> # @correction-mask: Bits within each nibble. Used in order of bits
> # set in the nibble-mask. Up to 4 nibbles may be covered.
> #
> +# @component-id: Device specific component identifier for the event.
> +# May describe a field replaceable sub-component of the device.
Identical to cxl-inject-general-media-event's argument, except ...
> +# See CXL r3.2 Table 8-58 DRAM Event Record.
... we don't have such a reference there. Should we?
> +#
> +# @is-comp-id-pldm: Flag represents device specific component identifier
> +# format is PLDM or not.
> +#
> +# @sub-channel: The sub-channel of the memory event location.
> +# See CXL r3.2 Table 8-58 DRAM Event Record.
> +#
> +# @cme-ev-flags: Advanced programmable corrected memory error
> +# threshold event flags.
> +# See CXL r3.2 Table 8-58 DRAM Event Record.
> +#
> +# @cvme-count: Corrected volatile memory error count at event.
> +# See CXL r3.2 Table 8-58 DRAM Event Record.
> +#
> +# @sub-type: Memory event sub-type.
> +# See CXL r3.2 Table 8-58 DRAM Event Record.
> +#
Same additions to cxl-inject-dram-event as in the previous patch to
cxl-inject-general-media-event, except this one also adds @component-id
(which already cxl-inject-general-media-event already had), and
@sub-channel.
See also my comment on duplication in review of PATCH 1.
> # Since: 8.1
> ##
> { 'command': 'cxl-inject-dram-event',
> @@ -181,7 +201,11 @@
> 'type': 'uint8', 'transaction-type': 'uint8',
> '*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
> '*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
> - '*column': 'uint16', '*correction-mask': [ 'uint64' ]
> + '*column': 'uint16', '*correction-mask': [ 'uint64' ],
> + '*component-id': 'str', '*is-comp-id-pldm':'uint8',
> + '*sub-channel':'uint8',
> + '*cme-ev-flags':'uint8', '*cvme-count':'uint32',
> + 'sub-type':'uint8'
> }}
>
> ##
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH qemu v4 4/7] hw/cxl/events: Updates for rev3.2 memory module event record
2025-07-21 17:22 [PATCH qemu v4 0/7] hw/cxl: Update CXL events to rev3.2 and add maintenance support for memory repair features shiju.jose
` (2 preceding siblings ...)
2025-07-21 17:22 ` [PATCH qemu v4 3/7] hw/cxl/events: Updates for rev3.2 DRAM " shiju.jose
@ 2025-07-21 17:22 ` shiju.jose
2025-08-06 8:08 ` Markus Armbruster
2025-07-21 17:22 ` [PATCH qemu v4 5/7] hw/cxl/cxl-mailbox-utils: Move declaration of scrub and ECS feature attributes in cmd_features_set_feature() shiju.jose
` (2 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: shiju.jose @ 2025-07-21 17:22 UTC (permalink / raw)
To: qemu-devel, linux-cxl, jonathan.cameron, fan.ni, dave
Cc: linuxarm, shiju.jose
From: Shiju Jose <shiju.jose@huawei.com>
CXL spec rev3.2 section 8.2.10.2.1.3 Table 8-50, memory module
event record has updated with following new fields.
1. Validity Flags
2. Component Identifier
3. Device Event Sub-Type
Add updates for the above spec changes in the CXL memory module
event reporting and QMP command to inject memory module event.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
hw/mem/cxl_type3.c | 20 ++++++++++++++++++++
hw/mem/cxl_type3_stubs.c | 4 ++++
include/hw/cxl/cxl_events.h | 7 +++++--
qapi/cxl.json | 14 +++++++++++++-
4 files changed, 42 insertions(+), 3 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index afe5ceb1c9..ab74395186 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1937,6 +1937,9 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
}
}
+#define CXL_MMER_VALID_COMPONENT BIT(0)
+#define CXL_MMER_VALID_COMPONENT_ID_FORMAT BIT(1)
+
void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
uint32_t flags, bool has_maint_op_class,
uint8_t maint_op_class,
@@ -1953,11 +1956,16 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
uint32_t dirty_shutdown_count,
uint32_t corrected_volatile_error_count,
uint32_t corrected_persist_error_count,
+ const char *component_id,
+ bool has_comp_id_pldm,
+ uint8_t is_comp_id_pldm,
+ uint8_t sub_type,
Error **errp)
{
Object *obj = object_resolve_path(path, NULL);
CXLEventMemoryModule module;
CXLEventRecordHdr *hdr = &module.hdr;
+ uint16_t valid_flags = 0;
CXLDeviceState *cxlds;
CXLType3Dev *ct3d;
uint8_t enc_log;
@@ -2000,6 +2008,18 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
stl_le_p(&module.corrected_persistent_error_count,
corrected_persist_error_count);
+ if (component_id) {
+ strncpy((char *)module.component_id, component_id,
+ sizeof(module.component_id) - 1);
+ valid_flags |= CXL_MMER_VALID_COMPONENT;
+ if (has_comp_id_pldm && is_comp_id_pldm) {
+ valid_flags |= CXL_MMER_VALID_COMPONENT_ID_FORMAT;
+ }
+ }
+ module.sub_type = sub_type;
+
+ stw_le_p(&module.validity_flags, valid_flags);
+
if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&module)) {
cxl_event_irq_assert(ct3d);
}
diff --git a/hw/mem/cxl_type3_stubs.c b/hw/mem/cxl_type3_stubs.c
index c3cd97b5b7..1e78cfd0ef 100644
--- a/hw/mem/cxl_type3_stubs.c
+++ b/hw/mem/cxl_type3_stubs.c
@@ -78,6 +78,10 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
uint32_t dirty_shutdown_count,
uint32_t corrected_volatile_error_count,
uint32_t corrected_persist_error_count,
+ const char *component_id,
+ bool has_comp_id_pldm,
+ uint8_t is_comp_id_pldm,
+ uint8_t sub_type,
Error **errp) {}
void qmp_cxl_inject_poison(const char *path, uint64_t start, uint64_t length,
diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
index a3c5f2ec20..4a7836ad72 100644
--- a/include/hw/cxl/cxl_events.h
+++ b/include/hw/cxl/cxl_events.h
@@ -166,7 +166,7 @@ typedef struct CXLEventDram {
/*
* Memory Module Event Record
- * CXL r3.1 Section 8.2.9.2.1.3: Table 8-47
+ * CXL r3.2 Section 8.2.10.2.1.3: Table 8-59
* All fields little endian.
*/
typedef struct CXLEventMemoryModule {
@@ -180,7 +180,10 @@ typedef struct CXLEventMemoryModule {
uint32_t dirty_shutdown_count;
uint32_t corrected_volatile_error_count;
uint32_t corrected_persistent_error_count;
- uint8_t reserved[0x3d];
+ uint16_t validity_flags;
+ uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
+ uint8_t sub_type;
+ uint8_t reserved[0x2a];
} QEMU_PACKED CXLEventMemoryModule;
/*
diff --git a/qapi/cxl.json b/qapi/cxl.json
index f84088c0b9..118dec5362 100644
--- a/qapi/cxl.json
+++ b/qapi/cxl.json
@@ -261,6 +261,16 @@
# @corrected-persistent-error-count: Total number of correctable
# errors in persistent memory
#
+# @component-id: Device specific component identifier for the event.
+# May describe a field replaceable sub-component of the device.
+# See CXL r3.2 Table 8-59 Memory Module Event Record.
+#
+# @is-comp-id-pldm: Flag represents device specific component identifier
+# format is PLDM or not.
+#
+# @sub-type: Device event sub-type.
+# See CXL r3.2 Table 8-59 Memory Module Event Record.
+#
# Since: 8.1
##
{ 'command': 'cxl-inject-memory-module-event',
@@ -272,7 +282,9 @@
'life-used': 'uint8', 'temperature' : 'int16',
'dirty-shutdown-count': 'uint32',
'corrected-volatile-error-count': 'uint32',
- 'corrected-persistent-error-count': 'uint32'
+ 'corrected-persistent-error-count': 'uint32',
+ '*component-id': 'str', '*is-comp-id-pldm':'uint8',
+ 'sub-type':'uint8'
}}
##
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH qemu v4 4/7] hw/cxl/events: Updates for rev3.2 memory module event record
2025-07-21 17:22 ` [PATCH qemu v4 4/7] hw/cxl/events: Updates for rev3.2 memory module " shiju.jose
@ 2025-08-06 8:08 ` Markus Armbruster
0 siblings, 0 replies; 17+ messages in thread
From: Markus Armbruster @ 2025-08-06 8:08 UTC (permalink / raw)
To: shiju.jose--- via
Cc: linux-cxl, jonathan.cameron, fan.ni, dave, shiju.jose, linuxarm
shiju.jose--- via <qemu-devel@nongnu.org> writes:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> CXL spec rev3.2 section 8.2.10.2.1.3 Table 8-50, memory module
> event record has updated with following new fields.
> 1. Validity Flags
> 2. Component Identifier
> 3. Device Event Sub-Type
>
> Add updates for the above spec changes in the CXL memory module
> event reporting and QMP command to inject memory module event.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
[...]
> diff --git a/qapi/cxl.json b/qapi/cxl.json
> index f84088c0b9..118dec5362 100644
> --- a/qapi/cxl.json
> +++ b/qapi/cxl.json
> @@ -261,6 +261,16 @@
> # @corrected-persistent-error-count: Total number of correctable
> # errors in persistent memory
> #
> +# @component-id: Device specific component identifier for the event.
> +# May describe a field replaceable sub-component of the device.
> +# See CXL r3.2 Table 8-59 Memory Module Event Record.
> +#
> +# @is-comp-id-pldm: Flag represents device specific component identifier
> +# format is PLDM or not.
> +#
> +# @sub-type: Device event sub-type.
> +# See CXL r3.2 Table 8-59 Memory Module Event Record.
> +#
> # Since: 8.1
> ##
> { 'command': 'cxl-inject-memory-module-event',
Again, partial copy of stuff the previous two patches added to related
commands.
> @@ -272,7 +282,9 @@
> 'life-used': 'uint8', 'temperature' : 'int16',
> 'dirty-shutdown-count': 'uint32',
> 'corrected-volatile-error-count': 'uint32',
> - 'corrected-persistent-error-count': 'uint32'
> + 'corrected-persistent-error-count': 'uint32',
> + '*component-id': 'str', '*is-comp-id-pldm':'uint8',
> + 'sub-type':'uint8'
> }}
>
> ##
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH qemu v4 5/7] hw/cxl/cxl-mailbox-utils: Move declaration of scrub and ECS feature attributes in cmd_features_set_feature()
2025-07-21 17:22 [PATCH qemu v4 0/7] hw/cxl: Update CXL events to rev3.2 and add maintenance support for memory repair features shiju.jose
` (3 preceding siblings ...)
2025-07-21 17:22 ` [PATCH qemu v4 4/7] hw/cxl/events: Updates for rev3.2 memory module " shiju.jose
@ 2025-07-21 17:22 ` shiju.jose
2025-07-21 17:22 ` [PATCH qemu v4 6/7] hw/cxl: Add Maintenance support shiju.jose
2025-07-21 17:22 ` [PATCH qemu v4 7/7] hw/cxl: Add emulation for memory sparing control feature shiju.jose
6 siblings, 0 replies; 17+ messages in thread
From: shiju.jose @ 2025-07-21 17:22 UTC (permalink / raw)
To: qemu-devel, linux-cxl, jonathan.cameron, fan.ni, dave
Cc: linuxarm, shiju.jose
From: Shiju Jose <shiju.jose@huawei.com>
Move the declaration of scrub and ECS feature attributes in
cmd_features_set_feature() to the local scope where they are used.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
hw/cxl/cxl-mailbox-utils.c | 17 +++++++----------
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 8f62ea9b54..ce02ae8528 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -1350,10 +1350,6 @@ static CXLRetCode cmd_features_set_feature(const struct cxl_cmd *cmd,
CXLCCI *cci)
{
CXLSetFeatureInHeader *hdr = (void *)payload_in;
- CXLMemPatrolScrubWriteAttrs *ps_write_attrs;
- CXLMemPatrolScrubSetFeature *ps_set_feature;
- CXLMemECSWriteAttrs *ecs_write_attrs;
- CXLMemECSSetFeature *ecs_set_feature;
CXLSetFeatureInfo *set_feat_info;
uint16_t bytes_to_copy = 0;
uint8_t data_transfer_flag;
@@ -1395,13 +1391,14 @@ static CXLRetCode cmd_features_set_feature(const struct cxl_cmd *cmd,
}
if (qemu_uuid_is_equal(&hdr->uuid, &patrol_scrub_uuid)) {
+ CXLMemPatrolScrubSetFeature *ps_set_feature = (void *)payload_in;
+ CXLMemPatrolScrubWriteAttrs *ps_write_attrs =
+ &ps_set_feature->feat_data;
+
if (hdr->version != CXL_MEMDEV_PS_SET_FEATURE_VERSION) {
return CXL_MBOX_UNSUPPORTED;
}
- ps_set_feature = (void *)payload_in;
- ps_write_attrs = &ps_set_feature->feat_data;
-
if ((uint32_t)hdr->offset + bytes_to_copy >
sizeof(ct3d->patrol_scrub_wr_attrs)) {
return CXL_MBOX_INVALID_PAYLOAD_LENGTH;
@@ -1422,13 +1419,13 @@ static CXLRetCode cmd_features_set_feature(const struct cxl_cmd *cmd,
}
} else if (qemu_uuid_is_equal(&hdr->uuid,
&ecs_uuid)) {
+ CXLMemECSSetFeature *ecs_set_feature = (void *)payload_in;
+ CXLMemECSWriteAttrs *ecs_write_attrs = ecs_set_feature->feat_data;
+
if (hdr->version != CXL_ECS_SET_FEATURE_VERSION) {
return CXL_MBOX_UNSUPPORTED;
}
- ecs_set_feature = (void *)payload_in;
- ecs_write_attrs = ecs_set_feature->feat_data;
-
if ((uint32_t)hdr->offset + bytes_to_copy >
sizeof(ct3d->ecs_wr_attrs)) {
return CXL_MBOX_INVALID_PAYLOAD_LENGTH;
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH qemu v4 6/7] hw/cxl: Add Maintenance support
2025-07-21 17:22 [PATCH qemu v4 0/7] hw/cxl: Update CXL events to rev3.2 and add maintenance support for memory repair features shiju.jose
` (4 preceding siblings ...)
2025-07-21 17:22 ` [PATCH qemu v4 5/7] hw/cxl/cxl-mailbox-utils: Move declaration of scrub and ECS feature attributes in cmd_features_set_feature() shiju.jose
@ 2025-07-21 17:22 ` shiju.jose
2025-07-25 13:26 ` Jonathan Cameron
2025-07-21 17:22 ` [PATCH qemu v4 7/7] hw/cxl: Add emulation for memory sparing control feature shiju.jose
6 siblings, 1 reply; 17+ messages in thread
From: shiju.jose @ 2025-07-21 17:22 UTC (permalink / raw)
To: qemu-devel, linux-cxl, jonathan.cameron, fan.ni, dave
Cc: linuxarm, shiju.jose
From: Davidlohr Bueso <dave@stgolabs.net>
This adds initial support for the Maintenance command, specifically
the soft and hard PPR operations on a dpa. The implementation allows
to be executed at runtime, therefore semantically, data is retained
and CXL.mem requests are correctly processed.
Keep track of the requests upon a general media or DRAM event.
Post Package Repair (PPR) maintenance operations may be supported by CXL
devices that implement CXL.mem protocol. A PPR maintenance operation
requests the CXL device to perform a repair operation on its media.
For example, a CXL device with DRAM components that support PPR features
may implement PPR Maintenance operations. DRAM components may support two
types of PPR, hard PPR (hPPR), for a permanent row repair, and Soft PPR
(sPPR), for a temporary row repair. Soft PPR is much faster than hPPR,
but the repair is lost with a power cycle.
CXL spec 3.2 section 8.2.10.7.1.2 describes the device's sPPR (soft PPR)
maintenance operation and section 8.2.10.7.1.3 describes the device's
hPPR (hard PPR) maintenance operation feature.
CXL spec 3.2 section 8.2.10.7.2.1 describes the sPPR feature discovery and
configuration.
CXL spec 3.2 section 8.2.10.7.2.2 describes the hPPR feature discovery and
configuration.
CXL spec 3.2 section 8.2.10.2.1.4 Table 8-60 describes the Memory Sparing
Event Record.
Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Co-developed-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
hw/cxl/cxl-mailbox-utils.c | 243 +++++++++++++++++++++++++++++++++++-
hw/mem/cxl_type3.c | 59 +++++++++
include/hw/cxl/cxl_device.h | 102 +++++++++++++++
include/hw/cxl/cxl_events.h | 42 +++++++
4 files changed, 444 insertions(+), 2 deletions(-)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index ce02ae8528..4dae357f7d 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -85,6 +85,8 @@ enum {
#define GET_SUPPORTED 0x0
#define GET_FEATURE 0x1
#define SET_FEATURE 0x2
+ MAINTENANCE = 0x06,
+ #define PERFORM 0x0
IDENTIFY = 0x40,
#define MEMORY_DEVICE 0x0
CCLS = 0x41,
@@ -1110,8 +1112,8 @@ typedef struct CXLSupportedFeatureEntry {
#define CXL_FEAT_ENTRY_ATTR_FLAG_CHANGABLE BIT(0)
#define CXL_FEAT_ENTRY_ATTR_FLAG_DEEPEST_RESET_PERSISTENCE_MASK GENMASK(3, 1)
#define CXL_FEAT_ENTRY_ATTR_FLAG_PERSIST_ACROSS_FIRMWARE_UPDATE BIT(4)
-#define CXL_FEAT_ENTRY_ATTR_FLAG_SUPPORT_DEFAULT_SELECTION BIT(5)
-#define CXL_FEAT_ENTRY_ATTR_FLAG_SUPPORT_SAVED_SELECTION BIT(6)
+#define CXL_FEAT_ENTRY_ATTR_FLAG_SUPPORT_DEFAULT_SEL BIT(5)
+#define CXL_FEAT_ENTRY_ATTR_FLAG_SUPPORT_SAVED_SEL BIT(6)
/* Supported Feature Entry : set feature effects */
#define CXL_FEAT_ENTRY_SFE_CONFIG_CHANGE_COLD_RESET BIT(0)
@@ -1130,6 +1132,8 @@ typedef struct CXLSupportedFeatureEntry {
enum CXL_SUPPORTED_FEATURES_LIST {
CXL_FEATURE_PATROL_SCRUB = 0,
CXL_FEATURE_ECS,
+ CXL_FEATURE_SPPR,
+ CXL_FEATURE_HPPR,
CXL_FEATURE_MAX
};
@@ -1171,6 +1175,28 @@ enum CXL_SET_FEATURE_FLAG_DATA_TRANSFER {
};
#define CXL_SET_FEAT_DATA_SAVED_ACROSS_RESET BIT(3)
+/* CXL r3.2 section 8.2.10.7.2.1: sPPR Feature Discovery and Configuration */
+static const QemuUUID soft_ppr_uuid = {
+ .data = UUID(0x892ba475, 0xfad8, 0x474e, 0x9d, 0x3e,
+ 0x69, 0x2c, 0x91, 0x75, 0x68, 0xbb)
+};
+
+typedef struct CXLMemSoftPPRSetFeature {
+ CXLSetFeatureInHeader hdr;
+ CXLMemSoftPPRWriteAttrs feat_data;
+} QEMU_PACKED QEMU_ALIGNED(16) CXLMemSoftPPRSetFeature;
+
+/* CXL r3.2 section 8.2.10.7.2.2: hPPR Feature Discovery and Configuration */
+static const QemuUUID hard_ppr_uuid = {
+ .data = UUID(0x80ea4521, 0x786f, 0x4127, 0xaf, 0xb1,
+ 0xec, 0x74, 0x59, 0xfb, 0x0e, 0x24)
+};
+
+typedef struct CXLMemHardPPRSetFeature {
+ CXLSetFeatureInHeader hdr;
+ CXLMemHardPPRWriteAttrs feat_data;
+} QEMU_PACKED QEMU_ALIGNED(16) CXLMemHardPPRSetFeature;
+
/* CXL r3.1 section 8.2.9.9.11.1: Device Patrol Scrub Control Feature */
static const QemuUUID patrol_scrub_uuid = {
.data = UUID(0x96dad7d6, 0xfde8, 0x482b, 0xa7, 0x33,
@@ -1234,6 +1260,38 @@ static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,
for (entry = 0, index = get_feats_in->start_index;
entry < req_entries; index++) {
switch (index) {
+ case CXL_FEATURE_SPPR:
+ /* Fill supported feature entry for soft-PPR */
+ get_feats_out->feat_entries[entry++] =
+ (struct CXLSupportedFeatureEntry) {
+ .uuid = soft_ppr_uuid,
+ .feat_index = index,
+ .get_feat_size = sizeof(CXLMemSoftPPRReadAttrs),
+ .set_feat_size = sizeof(CXLMemSoftPPRWriteAttrs),
+ .attr_flags = CXL_FEAT_ENTRY_ATTR_FLAG_CHANGABLE |
+ CXL_FEAT_ENTRY_ATTR_FLAG_SUPPORT_DEFAULT_SEL,
+ .get_feat_version = CXL_MEMDEV_SPPR_GET_FEATURE_VERSION,
+ .set_feat_version = CXL_MEMDEV_SPPR_SET_FEATURE_VERSION,
+ .set_feat_effects = CXL_FEAT_ENTRY_SFE_IMMEDIATE_CONFIG_CHANGE |
+ CXL_FEAT_ENTRY_SFE_CEL_VALID,
+ };
+ break;
+ case CXL_FEATURE_HPPR:
+ /* Fill supported feature entry for hard-PPR */
+ get_feats_out->feat_entries[entry++] =
+ (struct CXLSupportedFeatureEntry) {
+ .uuid = hard_ppr_uuid,
+ .feat_index = index,
+ .get_feat_size = sizeof(CXLMemHardPPRReadAttrs),
+ .set_feat_size = sizeof(CXLMemHardPPRWriteAttrs),
+ .attr_flags = CXL_FEAT_ENTRY_ATTR_FLAG_CHANGABLE |
+ CXL_FEAT_ENTRY_ATTR_FLAG_SUPPORT_DEFAULT_SEL,
+ .get_feat_version = CXL_MEMDEV_HPPR_GET_FEATURE_VERSION,
+ .set_feat_version = CXL_MEMDEV_HPPR_SET_FEATURE_VERSION,
+ .set_feat_effects = CXL_FEAT_ENTRY_SFE_IMMEDIATE_CONFIG_CHANGE |
+ CXL_FEAT_ENTRY_SFE_CEL_VALID,
+ };
+ break;
case CXL_FEATURE_PATROL_SCRUB:
/* Fill supported feature entry for device patrol scrub control */
get_feats_out->feat_entries[entry++] =
@@ -1332,6 +1390,26 @@ static CXLRetCode cmd_features_get_feature(const struct cxl_cmd *cmd,
memcpy(payload_out,
(uint8_t *)&ct3d->ecs_attrs + get_feature->offset,
bytes_to_copy);
+ } else if (qemu_uuid_is_equal(&get_feature->uuid, &soft_ppr_uuid)) {
+ if (get_feature->offset >= sizeof(CXLMemSoftPPRReadAttrs)) {
+ return CXL_MBOX_INVALID_INPUT;
+ }
+ bytes_to_copy = sizeof(CXLMemSoftPPRReadAttrs) -
+ get_feature->offset;
+ bytes_to_copy = MIN(bytes_to_copy, get_feature->count);
+ memcpy(payload_out,
+ (uint8_t *)&ct3d->soft_ppr_attrs + get_feature->offset,
+ bytes_to_copy);
+ } else if (qemu_uuid_is_equal(&get_feature->uuid, &hard_ppr_uuid)) {
+ if (get_feature->offset >= sizeof(CXLMemHardPPRReadAttrs)) {
+ return CXL_MBOX_INVALID_INPUT;
+ }
+ bytes_to_copy = sizeof(CXLMemHardPPRReadAttrs) -
+ get_feature->offset;
+ bytes_to_copy = MIN(bytes_to_copy, get_feature->count);
+ memcpy(payload_out,
+ (uint8_t *)&ct3d->hard_ppr_attrs + get_feature->offset,
+ bytes_to_copy);
} else {
return CXL_MBOX_UNSUPPORTED;
}
@@ -1443,6 +1521,46 @@ static CXLRetCode cmd_features_set_feature(const struct cxl_cmd *cmd,
ct3d->ecs_wr_attrs.fru_attrs[count].ecs_config & 0x1F;
}
}
+ } else if (qemu_uuid_is_equal(&hdr->uuid, &soft_ppr_uuid)) {
+ CXLMemSoftPPRSetFeature *sppr_set_feature = (void *)payload_in;
+ CXLMemSoftPPRWriteAttrs *sppr_write_attrs =
+ &sppr_set_feature->feat_data;
+
+ if (hdr->version != CXL_MEMDEV_SPPR_SET_FEATURE_VERSION) {
+ return CXL_MBOX_UNSUPPORTED;
+ }
+
+ memcpy((uint8_t *)&ct3d->soft_ppr_wr_attrs + hdr->offset,
+ sppr_write_attrs,
+ bytes_to_copy);
+ set_feat_info->data_size += bytes_to_copy;
+
+ if (data_transfer_flag == CXL_SET_FEATURE_FLAG_FULL_DATA_TRANSFER ||
+ data_transfer_flag == CXL_SET_FEATURE_FLAG_FINISH_DATA_TRANSFER) {
+ ct3d->soft_ppr_attrs.op_mode = ct3d->soft_ppr_wr_attrs.op_mode;
+ ct3d->soft_ppr_attrs.sppr_op_mode =
+ ct3d->soft_ppr_wr_attrs.sppr_op_mode;
+ }
+ } else if (qemu_uuid_is_equal(&hdr->uuid, &hard_ppr_uuid)) {
+ CXLMemHardPPRSetFeature *hppr_set_feature = (void *)payload_in;
+ CXLMemHardPPRWriteAttrs *hppr_write_attrs =
+ &hppr_set_feature->feat_data;
+
+ if (hdr->version != CXL_MEMDEV_HPPR_SET_FEATURE_VERSION) {
+ return CXL_MBOX_UNSUPPORTED;
+ }
+
+ memcpy((uint8_t *)&ct3d->hard_ppr_wr_attrs + hdr->offset,
+ hppr_write_attrs,
+ bytes_to_copy);
+ set_feat_info->data_size += bytes_to_copy;
+
+ if (data_transfer_flag == CXL_SET_FEATURE_FLAG_FULL_DATA_TRANSFER ||
+ data_transfer_flag == CXL_SET_FEATURE_FLAG_FINISH_DATA_TRANSFER) {
+ ct3d->hard_ppr_attrs.op_mode = ct3d->hard_ppr_wr_attrs.op_mode;
+ ct3d->hard_ppr_attrs.hppr_op_mode =
+ ct3d->hard_ppr_wr_attrs.hppr_op_mode;
+ }
} else {
return CXL_MBOX_UNSUPPORTED;
}
@@ -1455,6 +1573,10 @@ static CXLRetCode cmd_features_set_feature(const struct cxl_cmd *cmd,
memset(&ct3d->patrol_scrub_wr_attrs, 0, set_feat_info->data_size);
} else if (qemu_uuid_is_equal(&hdr->uuid, &ecs_uuid)) {
memset(&ct3d->ecs_wr_attrs, 0, set_feat_info->data_size);
+ } else if (qemu_uuid_is_equal(&hdr->uuid, &soft_ppr_uuid)) {
+ memset(&ct3d->soft_ppr_wr_attrs, 0, set_feat_info->data_size);
+ } else if (qemu_uuid_is_equal(&hdr->uuid, &hard_ppr_uuid)) {
+ memset(&ct3d->hard_ppr_wr_attrs, 0, set_feat_info->data_size);
}
set_feat_info->data_transfer_flag = 0;
set_feat_info->data_saved_across_reset = false;
@@ -1465,6 +1587,117 @@ static CXLRetCode cmd_features_set_feature(const struct cxl_cmd *cmd,
return CXL_MBOX_SUCCESS;
}
+static void cxl_mbox_create_mem_sparing_event_records(CXLType3Dev *ct3d,
+ uint8_t class, uint8_t sub_class)
+{
+ CXLEventSparing event_rec = {};
+
+ cxl_assign_event_header(&event_rec.hdr,
+ &sparing_uuid,
+ (1 << CXL_EVENT_TYPE_INFO),
+ sizeof(event_rec),
+ cxl_device_get_timestamp(&ct3d->cxl_dstate),
+ 1, class, 1, sub_class, 0, 0, 0, 0);
+
+ event_rec.flags = 0;
+ event_rec.result = 0;
+ event_rec.validity_flags = CXL_MSER_VALID_CHANNEL |
+ CXL_MSER_VALID_RANK |
+ CXL_MSER_VALID_NIB_MASK |
+ CXL_MSER_VALID_BANK_GROUP |
+ CXL_MSER_VALID_BANK |
+ CXL_MSER_VALID_ROW |
+ CXL_MSER_VALID_COLUMN |
+ CXL_MSER_VALID_SUB_CHANNEL;
+
+ event_rec.res_avail = 1;
+ event_rec.channel = 2;
+ event_rec.rank = 5;
+ st24_le_p(event_rec.nibble_mask, 0xA59C);
+ event_rec.bank_group = 2;
+ event_rec.bank = 4;
+ st24_le_p(event_rec.row, 13);
+ event_rec.column = 23;
+ event_rec.sub_channel = 7;
+
+ if (cxl_event_insert(&ct3d->cxl_dstate,
+ CXL_EVENT_TYPE_INFO,
+ (CXLEventRecordRaw *)&event_rec)) {
+ cxl_event_irq_assert(ct3d);
+ }
+}
+
+
+static void cxl_perform_ppr(CXLType3Dev *ct3d, uint64_t dpa)
+{
+ CXLMaintenance *ent, *next;
+
+ QLIST_FOREACH_SAFE(ent, &ct3d->maint_list, node, next) {
+ if (dpa == ent->dpa) {
+ QLIST_REMOVE(ent, node);
+ g_free(ent);
+ break;
+ }
+ }
+
+ /* Produce a Memory Sparing Event Record */
+ if (ct3d->soft_ppr_attrs.sppr_op_mode &
+ CXL_MEMDEV_SPPR_OP_MODE_MEM_SPARING_EV_REC_EN) {
+ cxl_mbox_create_mem_sparing_event_records(ct3d,
+ CXL_MEMDEV_MAINT_CLASS_SPARING,
+ CXL_MEMDEV_MAINT_SUBCLASS_CACHELINE_SPARING);
+ }
+}
+
+/* CXL r3.2 section 8.2.10.7.1 - Perform Maintenance (Opcode 0600h) */
+#define MAINTENANCE_PPR_QUERY_RESOURCES BIT(0)
+
+static CXLRetCode cmd_media_perform_maintenance(const struct cxl_cmd *cmd,
+ uint8_t *payload_in, size_t len_in,
+ uint8_t *payload_out, size_t *len_out,
+ CXLCCI *cci)
+{
+ struct {
+ uint8_t class;
+ uint8_t subclass;
+ union {
+ struct {
+ uint8_t flags;
+ uint64_t dpa;
+ uint8_t nibble_mask[3];
+ } QEMU_PACKED ppr;
+ };
+ } QEMU_PACKED *maint_in = (void *)payload_in;
+ CXLType3Dev *ct3d = CXL_TYPE3(cci->d);
+
+ if (maintenance_running(cci)) {
+ return CXL_MBOX_BUSY;
+ }
+
+ switch (maint_in->class) {
+ case CXL_MEMDEV_MAINT_CLASS_NO_OP:
+ return CXL_MBOX_SUCCESS; /* nop */
+ case CXL_MEMDEV_MAINT_CLASS_PPR:
+ if (maint_in->ppr.flags & MAINTENANCE_PPR_QUERY_RESOURCES) {
+ return CXL_MBOX_SUCCESS;
+ }
+
+ switch (maint_in->subclass) {
+ case CXL_MEMDEV_MAINT_SUBCLASS_SPPR:
+ case CXL_MEMDEV_MAINT_SUBCLASS_HPPR:
+ cxl_perform_ppr(ct3d, ldq_le_p(&maint_in->ppr.dpa));
+ return CXL_MBOX_SUCCESS;
+ default:
+ return CXL_MBOX_INVALID_INPUT;
+ }
+ break;
+ default:
+ return CXL_MBOX_INVALID_INPUT;
+ }
+
+ return CXL_MBOX_SUCCESS;
+}
+
/* CXL r3.1 Section 8.2.9.9.1.1: Identify Memory Device (Opcode 4000h) */
static CXLRetCode cmd_identify_memory_device(const struct cxl_cmd *cmd,
uint8_t *payload_in,
@@ -3761,6 +3994,12 @@ static const struct cxl_cmd cxl_cmd_set[256][256] = {
CXL_MBOX_IMMEDIATE_POLICY_CHANGE |
CXL_MBOX_IMMEDIATE_LOG_CHANGE |
CXL_MBOX_SECURITY_STATE_CHANGE)},
+ [MAINTENANCE][PERFORM] = { "MAINTENANCE_PERFORM",
+ cmd_media_perform_maintenance, ~0,
+ CXL_MBOX_IMMEDIATE_CONFIG_CHANGE |
+ CXL_MBOX_IMMEDIATE_DATA_CHANGE |
+ CXL_MBOX_IMMEDIATE_LOG_CHANGE |
+ CXL_MBOX_BACKGROUND_OPERATION },
[IDENTIFY][MEMORY_DEVICE] = { "IDENTIFY_MEMORY_DEVICE",
cmd_identify_memory_device, 0, 0 },
[CCLS][GET_PARTITION_INFO] = { "CCLS_GET_PARTITION_INFO",
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index ab74395186..cf166ea05e 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -964,6 +964,32 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
ct3d->ecs_attrs.fru_attrs[count].ecs_flags = 0;
}
+ /* Set default values for soft-PPR attributes */
+ ct3d->soft_ppr_attrs = (CXLMemSoftPPRReadAttrs) {
+ .max_maint_latency = 0x5, /* 100 ms */
+ .op_caps = 0, /* require host involvement */
+ .op_mode = 0,
+ .maint_op_class = CXL_MEMDEV_MAINT_CLASS_PPR,
+ .maint_op_subclass = CXL_MEMDEV_MAINT_SUBCLASS_SPPR,
+ .sppr_flags = CXL_MEMDEV_SPPR_DPA_SUPPORT_FLAG |
+ CXL_MEMDEV_SPPR_MEM_SPARING_EV_REC_CAP_FLAG,
+ .restriction_flags = 0,
+ .sppr_op_mode = CXL_MEMDEV_SPPR_OP_MODE_MEM_SPARING_EV_REC_EN
+ };
+
+ /* Set default value for hard-PPR attributes */
+ ct3d->hard_ppr_attrs = (CXLMemHardPPRReadAttrs) {
+ .max_maint_latency = 0x5, /* 100 ms */
+ .op_caps = 0, /* require host involvement */
+ .op_mode = 0,
+ .maint_op_class = CXL_MEMDEV_MAINT_CLASS_PPR,
+ .maint_op_subclass = CXL_MEMDEV_MAINT_SUBCLASS_HPPR,
+ .hppr_flags = CXL_MEMDEV_HPPR_DPA_SUPPORT_FLAG |
+ CXL_MEMDEV_HPPR_MEM_SPARING_EV_REC_CAP_FLAG,
+ .restriction_flags = 0,
+ .hppr_op_mode = CXL_MEMDEV_HPPR_OP_MODE_MEM_SPARING_EV_REC_EN
+ };
+
return;
err_release_cdat:
@@ -1667,6 +1693,21 @@ static int ct3d_qmp_cxl_event_log_enc(CxlEventLog log)
return -EINVAL;
}
}
+
+static void cxl_maintenance_insert(CXLType3Dev *ct3d, uint64_t dpa)
+{
+ CXLMaintenance *ent, *m;
+
+ QLIST_FOREACH(ent, &ct3d->maint_list, node) {
+ if (dpa == ent->dpa) {
+ return;
+ }
+ }
+ m = g_new0(CXLMaintenance, 1);
+ m->dpa = dpa;
+ QLIST_INSERT_HEAD(&ct3d->maint_list, m, node);
+}
+
/* Component ID is device specific. Define this as a string. */
void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
uint32_t flags, bool has_maint_op_class,
@@ -1715,6 +1756,11 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
error_setg(errp, "Unhandled error log type");
return;
}
+ if (rc == CXL_EVENT_TYPE_INFO &&
+ (flags & CXL_EVENT_REC_FLAGS_MAINT_NEEDED)) {
+ error_setg(errp, "Informational event cannot require maintenance");
+ return;
+ }
enc_log = rc;
memset(&gem, 0, sizeof(gem));
@@ -1773,6 +1819,10 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&gem)) {
cxl_event_irq_assert(ct3d);
}
+
+ if (flags & CXL_EVENT_REC_FLAGS_MAINT_NEEDED) {
+ cxl_maintenance_insert(ct3d, dpa);
+ }
}
#define CXL_DRAM_VALID_CHANNEL BIT(0)
@@ -1842,6 +1892,11 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
error_setg(errp, "Unhandled error log type");
return;
}
+ if (rc == CXL_EVENT_TYPE_INFO &&
+ (flags & CXL_EVENT_REC_FLAGS_MAINT_NEEDED)) {
+ error_setg(errp, "Informational event cannot require maintenance");
+ return;
+ }
enc_log = rc;
memset(&dram, 0, sizeof(dram));
@@ -1935,6 +1990,10 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&dram)) {
cxl_event_irq_assert(ct3d);
}
+
+ if (flags & CXL_EVENT_REC_FLAGS_MAINT_NEEDED) {
+ cxl_maintenance_insert(ct3d, dpa);
+ }
}
#define CXL_MMER_VALID_COMPONENT BIT(0)
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index b77b6b2499..947288bf0a 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -430,6 +430,12 @@ static inline bool cxl_dev_media_disabled(CXLDeviceState *cxl_dstate)
uint64_t dev_status_reg = cxl_dstate->mbox_reg_state64[R_CXL_MEM_DEV_STS];
return FIELD_EX64(dev_status_reg, CXL_MEM_DEV_STS, MEDIA_STATUS) == 0x3;
}
+
+static inline bool maintenance_running(CXLCCI *cci)
+{
+ return cci->bg.runtime && cci->bg.opcode == 0x0600;
+}
+
static inline bool scan_media_running(CXLCCI *cci)
{
return !!cci->bg.runtime && cci->bg.opcode == 0x4304;
@@ -443,6 +449,13 @@ typedef struct CXLError {
typedef QTAILQ_HEAD(, CXLError) CXLErrorList;
+typedef struct CXLMaintenance {
+ uint64_t dpa;
+ QLIST_ENTRY(CXLMaintenance) node;
+} CXLMaintenance;
+
+typedef QLIST_HEAD(, CXLMaintenance) CXLMaintenanceList;
+
typedef struct CXLPoison {
uint64_t start, length;
uint8_t type;
@@ -455,6 +468,87 @@ typedef struct CXLPoison {
typedef QLIST_HEAD(, CXLPoison) CXLPoisonList;
#define CXL_POISON_LIST_LIMIT 256
+/* CXL memory maintenance operation */
+/*
+ * CXL r3.2 section 8.2.10.7.2, Table 8-125: Mainteance Operation:
+ * Classes, Subclasses, and Feature UUIDs
+ */
+#define CXL_MEMDEV_MAINT_CLASS_NO_OP 0x0
+#define CXL_MEMDEV_MAINT_CLASS_PPR 0x1
+#define CXL_MEMDEV_MAINT_CLASS_SPARING 0x2
+#define CXL_MEMDEV_MAINT_CLASS_DEV_BUILT_IN_TEST 0x3
+
+#define CXL_MEMDEV_MAINT_SUBCLASS_SPPR 0x0
+#define CXL_MEMDEV_MAINT_SUBCLASS_HPPR 0x1
+
+#define CXL_MEMDEV_MAINT_SUBCLASS_CACHELINE_SPARING 0x0
+#define CXL_MEMDEV_MAINT_SUBCLASS_ROW_SPARING 0x1
+#define CXL_MEMDEV_MAINT_SUBCLASS_BANK_SPARING 0x2
+#define CXL_MEMDEV_MAINT_SUBCLASS_RANK_SPARING 0x3
+
+/* CXL memory Post Package Repair control attributes */
+/*
+ * CXL r3.2 section 8.2.10.7.2.1, Table 8-128 and 8-129:
+ * sPPR Feature Readable/Writable Attributes
+ */
+typedef struct CXLMemSoftPPRReadAttrs {
+ uint8_t max_maint_latency;
+ uint16_t op_caps;
+ uint16_t op_mode;
+ uint8_t maint_op_class;
+ uint8_t maint_op_subclass;
+ uint8_t rsvd[9];
+ uint8_t sppr_flags;
+ uint16_t restriction_flags;
+ uint8_t sppr_op_mode;
+} QEMU_PACKED CXLMemSoftPPRReadAttrs;
+
+typedef struct CXLMemSoftPPRWriteAttrs {
+ uint16_t op_mode;
+ uint8_t sppr_op_mode;
+} QEMU_PACKED CXLMemSoftPPRWriteAttrs;
+
+#define CXL_MEMDEV_SPPR_GET_FEATURE_VERSION 0x03
+#define CXL_MEMDEV_SPPR_SET_FEATURE_VERSION 0x03
+#define CXL_MEMDEV_SPPR_DPA_SUPPORT_FLAG BIT(0)
+#define CXL_MEMDEV_SPPR_NIBBLE_SUPPORT_FLAG BIT(1)
+#define CXL_MEMDEV_SPPR_MEM_SPARING_EV_REC_CAP_FLAG BIT(2)
+#define CXL_MEMDEV_SPPR_DEV_INITIATED_AT_BOOT_CAP_FLAG BIT(3)
+
+#define CXL_MEMDEV_SPPR_OP_MODE_MEM_SPARING_EV_REC_EN BIT(0)
+#define CXL_MEMDEV_SPPR_OP_MODE_DEV_INITIATED_AT_BOOT BIT(1)
+
+/*
+ * CXL r3.2 section 8.2.10.7.2.2, Table 8-131 and 8-132:
+ * hPPR Feature Readable/Writable Attributes
+ */
+typedef struct CXLMemHardPPRReadAttrs {
+ uint8_t max_maint_latency;
+ uint16_t op_caps;
+ uint16_t op_mode;
+ uint8_t maint_op_class;
+ uint8_t maint_op_subclass;
+ uint8_t rsvd[9];
+ uint8_t hppr_flags;
+ uint16_t restriction_flags;
+ uint8_t hppr_op_mode;
+} QEMU_PACKED CXLMemHardPPRReadAttrs;
+
+typedef struct CXLMemHardPPRWriteAttrs {
+ uint16_t op_mode;
+ uint8_t hppr_op_mode;
+} QEMU_PACKED CXLMemHardPPRWriteAttrs;
+
+#define CXL_MEMDEV_HPPR_GET_FEATURE_VERSION 0x03
+#define CXL_MEMDEV_HPPR_SET_FEATURE_VERSION 0x03
+#define CXL_MEMDEV_HPPR_DPA_SUPPORT_FLAG BIT(0)
+#define CXL_MEMDEV_HPPR_NIBBLE_SUPPORT_FLAG BIT(1)
+#define CXL_MEMDEV_HPPR_MEM_SPARING_EV_REC_CAP_FLAG BIT(2)
+#define CXL_MEMDEV_HPPR_DEV_INITIATED_AT_BOOT_CAP_FLAG BIT(3)
+
+#define CXL_MEMDEV_HPPR_OP_MODE_MEM_SPARING_EV_REC_EN BIT(0)
+#define CXL_MEMDEV_HPPR_OP_MODE_DEV_INITIATED_AT_BOOT BIT(1)
+
/* CXL memory device patrol scrub control attributes */
typedef struct CXLMemPatrolScrubReadAttrs {
uint8_t scrub_cycle_cap;
@@ -605,6 +699,9 @@ struct CXLType3Dev {
/* Error injection */
CXLErrorList error_list;
+ /* Keep track of maintenance requests */
+ CXLMaintenanceList maint_list;
+
/* Poison Injection - cache */
CXLPoisonList poison_list;
unsigned int poison_list_cnt;
@@ -617,6 +714,11 @@ struct CXLType3Dev {
CXLSetFeatureInfo set_feat_info;
+ /* PPR control attributes */
+ CXLMemSoftPPRReadAttrs soft_ppr_attrs;
+ CXLMemSoftPPRWriteAttrs soft_ppr_wr_attrs;
+ CXLMemHardPPRReadAttrs hard_ppr_attrs;
+ CXLMemHardPPRWriteAttrs hard_ppr_wr_attrs;
/* Patrol scrub control attributes */
CXLMemPatrolScrubReadAttrs patrol_scrub_attrs;
CXLMemPatrolScrubWriteAttrs patrol_scrub_wr_attrs;
diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
index 4a7836ad72..3052bc9f18 100644
--- a/include/hw/cxl/cxl_events.h
+++ b/include/hw/cxl/cxl_events.h
@@ -219,4 +219,46 @@ typedef enum CXLDCEventType {
DC_EVENT_CAPACITY_RELEASED = 0x5,
} CXLDCEventType;
+/*
+ * CXL r3.2 section Table 8-60: Memory Sparing Event Record
+ * All fields little endian.
+ */
+#define CXL_MSER_VALID_CHANNEL BIT(0)
+#define CXL_MSER_VALID_RANK BIT(1)
+#define CXL_MSER_VALID_NIB_MASK BIT(2)
+#define CXL_MSER_VALID_BANK_GROUP BIT(3)
+#define CXL_MSER_VALID_BANK BIT(4)
+#define CXL_MSER_VALID_ROW BIT(5)
+#define CXL_MSER_VALID_COLUMN BIT(6)
+#define CXL_MSER_VALID_COMP_ID BIT(7)
+#define CXL_MSER_VALID_COMP_ID_FORMAT BIT(8)
+#define CXL_MSER_VALID_SUB_CHANNEL BIT(9)
+
+typedef struct CXLEventSparing {
+ CXLEventRecordHdr hdr;
+ uint8_t maint_op_class;
+ uint8_t maint_op_subclass;
+ uint8_t flags;
+ uint8_t result;
+ uint16_t validity_flags;
+ uint8_t reserved1[6];
+ uint16_t res_avail;
+ uint8_t channel;
+ uint8_t rank;
+ uint8_t nibble_mask[3];
+ uint8_t bank_group;
+ uint8_t bank;
+ uint8_t row[3];
+ uint16_t column;
+ uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
+ uint8_t sub_channel;
+ uint8_t reserved2[0x25];
+} QEMU_PACKED CXLEventSparing;
+
+/* CXL r3.2 Table 8-60: Memory Sparing Event Record */
+static const QemuUUID sparing_uuid = {
+ .data = UUID(0xe71f3a40, 0x2d29, 0x4092, 0x8a, 0x39,
+ 0x4d, 0x1c, 0x96, 0x6c, 0x7c, 0x65),
+};
+
#endif /* CXL_EVENTS_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH qemu v4 6/7] hw/cxl: Add Maintenance support
2025-07-21 17:22 ` [PATCH qemu v4 6/7] hw/cxl: Add Maintenance support shiju.jose
@ 2025-07-25 13:26 ` Jonathan Cameron
0 siblings, 0 replies; 17+ messages in thread
From: Jonathan Cameron @ 2025-07-25 13:26 UTC (permalink / raw)
To: shiju.jose; +Cc: qemu-devel, linux-cxl, fan.ni, dave, linuxarm
On Mon, 21 Jul 2025 18:22:27 +0100
<shiju.jose@huawei.com> wrote:
> From: Davidlohr Bueso <dave@stgolabs.net>
I tweaked the title to mention Post Package Repair. If anyone is ever
looking for that particular maintenance command they might want to know
it is in here from the title.
>
> This adds initial support for the Maintenance command, specifically
> the soft and hard PPR operations on a dpa. The implementation allows
> to be executed at runtime, therefore semantically, data is retained
> and CXL.mem requests are correctly processed.
>
> Keep track of the requests upon a general media or DRAM event.
>
> Post Package Repair (PPR) maintenance operations may be supported by CXL
> devices that implement CXL.mem protocol. A PPR maintenance operation
> requests the CXL device to perform a repair operation on its media.
> For example, a CXL device with DRAM components that support PPR features
> may implement PPR Maintenance operations. DRAM components may support two
> types of PPR, hard PPR (hPPR), for a permanent row repair, and Soft PPR
> (sPPR), for a temporary row repair. Soft PPR is much faster than hPPR,
> but the repair is lost with a power cycle.
>
> CXL spec 3.2 section 8.2.10.7.1.2 describes the device's sPPR (soft PPR)
> maintenance operation and section 8.2.10.7.1.3 describes the device's
> hPPR (hard PPR) maintenance operation feature.
>
> CXL spec 3.2 section 8.2.10.7.2.1 describes the sPPR feature discovery and
> configuration.
>
> CXL spec 3.2 section 8.2.10.7.2.2 describes the hPPR feature discovery and
> configuration.
>
> CXL spec 3.2 section 8.2.10.2.1.4 Table 8-60 describes the Memory Sparing
> Event Record.
>
> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
> Co-developed-by: Shiju Jose <shiju.jose@huawei.com>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
2x SoB for Shiju.
Main question I have on this is why we currently track things marked
for maintenance in injected error records, but don't act on that in any
way. I'm also thinking we could easily pass on any provided geometry so
the sparing record reflects what was injected if that's where it came from.
If we do PPR on something not injected we might still want to make some
plausible geometry up.
> +static void cxl_mbox_create_mem_sparing_event_records(CXLType3Dev *ct3d,
> + uint8_t class, uint8_t sub_class)
> +{
> + CXLEventSparing event_rec = {};
> +
> + cxl_assign_event_header(&event_rec.hdr,
> + &sparing_uuid,
> + (1 << CXL_EVENT_TYPE_INFO),
> + sizeof(event_rec),
> + cxl_device_get_timestamp(&ct3d->cxl_dstate),
> + 1, class, 1, sub_class, 0, 0, 0, 0);
> +
> + event_rec.flags = 0;
> + event_rec.result = 0;
> + event_rec.validity_flags = CXL_MSER_VALID_CHANNEL |
> + CXL_MSER_VALID_RANK |
> + CXL_MSER_VALID_NIB_MASK |
> + CXL_MSER_VALID_BANK_GROUP |
> + CXL_MSER_VALID_BANK |
> + CXL_MSER_VALID_ROW |
> + CXL_MSER_VALID_COLUMN |
> + CXL_MSER_VALID_SUB_CHANNEL;
> +
> + event_rec.res_avail = 1;
> + event_rec.channel = 2;
> + event_rec.rank = 5;
> + st24_le_p(event_rec.nibble_mask, 0xA59C);
> + event_rec.bank_group = 2;
> + event_rec.bank = 4;
> + st24_le_p(event_rec.row, 13);
> + event_rec.column = 23;
> + event_rec.sub_channel = 7;
At some point we should cycle back and make up some 'geometry' for the
memory so we can map different DPAs to different places. This is fine
for now though.
> +
> + if (cxl_event_insert(&ct3d->cxl_dstate,
> + CXL_EVENT_TYPE_INFO,
> + (CXLEventRecordRaw *)&event_rec)) {
> + cxl_event_irq_assert(ct3d);
> + }
> +}
> +
> +
> +static void cxl_perform_ppr(CXLType3Dev *ct3d, uint64_t dpa)
> +{
> + CXLMaintenance *ent, *next;
> +
> + QLIST_FOREACH_SAFE(ent, &ct3d->maint_list, node, next) {
If we did want to generate the right geometry to match the injected
event we'd want to retrieve it here (having stashed it in the ent)
> + if (dpa == ent->dpa) {
> + QLIST_REMOVE(ent, node);
What is this actually for at the moment? We track them on a list but
don't enforce anything with it? I don't think we should enforce this
as you can issue PPR on stuff that was never in error if you like.
> + g_free(ent);
> + break;
> + }
> + }
> +
> + /* Produce a Memory Sparing Event Record */
> + if (ct3d->soft_ppr_attrs.sppr_op_mode &
> + CXL_MEMDEV_SPPR_OP_MODE_MEM_SPARING_EV_REC_EN) {
> + cxl_mbox_create_mem_sparing_event_records(ct3d,
> + CXL_MEMDEV_MAINT_CLASS_SPARING,
> + CXL_MEMDEV_MAINT_SUBCLASS_CACHELINE_SPARING);
> + }
> +}
> /* Component ID is device specific. Define this as a string. */
> void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
> uint32_t flags, bool has_maint_op_class,
> @@ -1715,6 +1756,11 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
> error_setg(errp, "Unhandled error log type");
> return;
> }
> + if (rc == CXL_EVENT_TYPE_INFO &&
> + (flags & CXL_EVENT_REC_FLAGS_MAINT_NEEDED)) {
> + error_setg(errp, "Informational event cannot require maintenance");
> + return;
> + }
> enc_log = rc;
>
> memset(&gem, 0, sizeof(gem));
> @@ -1773,6 +1819,10 @@ void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
> if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&gem)) {
> cxl_event_irq_assert(ct3d);
> }
> +
> + if (flags & CXL_EVENT_REC_FLAGS_MAINT_NEEDED) {
> + cxl_maintenance_insert(ct3d, dpa);
Same as below.
> + }
>
> memset(&dram, 0, sizeof(dram));
> @@ -1935,6 +1990,10 @@ void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log,
> if (cxl_event_insert(cxlds, enc_log, (CXLEventRecordRaw *)&dram)) {
> cxl_event_irq_assert(ct3d);
> }
> +
> + if (flags & CXL_EVENT_REC_FLAGS_MAINT_NEEDED) {
> + cxl_maintenance_insert(ct3d, dpa);
We make up the geometry details for the sparing record, but we 'could'
store them here if they were injected and hence spit out an appropriate
sparing record?
Do you think it's worth doing at this stage?
Jonathan
> + }
> }
>
> #define CXL_MMER_VALID_COMPONENT BIT(0)
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH qemu v4 7/7] hw/cxl: Add emulation for memory sparing control feature
2025-07-21 17:22 [PATCH qemu v4 0/7] hw/cxl: Update CXL events to rev3.2 and add maintenance support for memory repair features shiju.jose
` (5 preceding siblings ...)
2025-07-21 17:22 ` [PATCH qemu v4 6/7] hw/cxl: Add Maintenance support shiju.jose
@ 2025-07-21 17:22 ` shiju.jose
2025-07-25 13:31 ` Jonathan Cameron
6 siblings, 1 reply; 17+ messages in thread
From: shiju.jose @ 2025-07-21 17:22 UTC (permalink / raw)
To: qemu-devel, linux-cxl, jonathan.cameron, fan.ni, dave
Cc: linuxarm, shiju.jose
From: Shiju Jose <shiju.jose@huawei.com>
Memory sparing is defined as a repair function that replaces a portion of
memory with a portion of functional memory at that same DPA. The
subclasses for this operation vary in terms of the scope of the sparing
being performed. The Cacheline sparing subclass refers to a sparing
action that can replace a full cacheline. Row sparing is provided as an
alternative to PPR sparing functions and its scope is that of a single
DDR row. Bank sparing allows an entire bank to be replaced. Rank sparing
is defined as an operation in which an entire DDR rank is replaced.
Memory sparing maintenance operations may be supported by CXL devices
that implement CXL.mem protocol. A sparing maintenance operation requests
the CXL device to perform a repair operation on its media.
For example, a CXL device with DRAM components that support memory sparing
features may implement sparing Maintenance operations.
The host may issue a query command by setting Query Resources flag in the
Input Payload (CXL Spec 3.2 Table 8-120) to determine availability of
sparing resources for a given address. In response to a query request,
the device shall report the resource availability by producing the Memory
Sparing Event Record (CXL Spec 3.2 Table 8-60) in which the Channel, Rank,
Nibble Mask, Bank Group, Bank, Row, Column, Sub-Channel fields are a copy
of the values specified in the request.
During the execution of a sparing maintenance operation, a CXL memory
device:
- May or may not retain data
- May or may not be able to process CXL.mem requests correctly.
These CXL memory device capabilities are specified by restriction flags
in the memory sparing feature readable attributes.
When a CXL device identifies error on a memory component, the device
may inform the host about the need for a memory sparing maintenance
operation by using DRAM event record, where the 'maintenance needed' flag
may set. The event record contains some of the DPA, Channel, Rank,
Nibble Mask, Bank Group, Bank, Row, Column, Sub-Channel fields that
should be repaired. The userspace tool requests for maintenance operation
if the 'maintenance needed' flag set in the CXL DRAM error record.
CXL spec 3.2 section 8.2.10.7.2.3 describes the memory sparing feature
discovery and configuration.
CXL spec 3.2 section 8.2.10.7.1.4 describes the device's memory sparing
maintenance operation feature.
Add emulation for CXL memory device memory sparing control feature
and memory sparing maintenance operation command.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
---
hw/cxl/cxl-mailbox-utils.c | 360 +++++++++++++++++++++++++++++++++---
hw/mem/cxl_type3.c | 44 +++++
include/hw/cxl/cxl_device.h | 33 ++++
include/hw/cxl/cxl_events.h | 5 +
4 files changed, 420 insertions(+), 22 deletions(-)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 4dae357f7d..891e687c7f 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -1134,6 +1134,10 @@ enum CXL_SUPPORTED_FEATURES_LIST {
CXL_FEATURE_ECS,
CXL_FEATURE_SPPR,
CXL_FEATURE_HPPR,
+ CXL_FEATURE_CACHELINE_SPARING,
+ CXL_FEATURE_ROW_SPARING,
+ CXL_FEATURE_BANK_SPARING,
+ CXL_FEATURE_RANK_SPARING,
CXL_FEATURE_MAX
};
@@ -1222,6 +1226,35 @@ typedef struct CXLMemECSSetFeature {
CXLMemECSWriteAttrs feat_data[];
} QEMU_PACKED QEMU_ALIGNED(16) CXLMemECSSetFeature;
+/*
+ * CXL r3.2 section 8.2.10.7.2.3:
+ * Memory Sparing Features Discovery and Configuration
+ */
+static const QemuUUID cacheline_sparing_uuid = {
+ .data = UUID(0x96C33386, 0x91dd, 0x44c7, 0x9e, 0xcb,
+ 0xfd, 0xaf, 0x65, 0x03, 0xba, 0xc4)
+};
+
+static const QemuUUID row_sparing_uuid = {
+ .data = UUID(0x450ebf67, 0xb135, 0x4f97, 0xa4, 0x98,
+ 0xc2, 0xd5, 0x7f, 0x27, 0x9b, 0xed)
+};
+
+static const QemuUUID bank_sparing_uuid = {
+ .data = UUID(0x78b79636, 0x90ac, 0x4b64, 0xa4, 0xef,
+ 0xfa, 0xac, 0x5d, 0x18, 0xa8, 0x63)
+};
+
+static const QemuUUID rank_sparing_uuid = {
+ .data = UUID(0x34dbaff5, 0x0552, 0x4281, 0x8f, 0x76,
+ 0xda, 0x0b, 0x5e, 0x7a, 0x76, 0xa7)
+};
+
+typedef struct CXLMemSparingSetFeature {
+ CXLSetFeatureInHeader hdr;
+ CXLMemSparingWriteAttrs feat_data;
+} QEMU_PACKED QEMU_ALIGNED(16) CXLMemSparingSetFeature;
+
/* CXL r3.1 section 8.2.9.6.1: Get Supported Features (Opcode 0500h) */
static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,
uint8_t *payload_in,
@@ -1322,6 +1355,70 @@ static CXLRetCode cmd_features_get_supported(const struct cxl_cmd *cmd,
CXL_FEAT_ENTRY_SFE_CEL_VALID,
};
break;
+ case CXL_FEATURE_CACHELINE_SPARING:
+ /* Fill supported feature entry for Cacheline Memory Sparing */
+ get_feats_out->feat_entries[entry++] =
+ (struct CXLSupportedFeatureEntry) {
+ .uuid = cacheline_sparing_uuid,
+ .feat_index = index,
+ .get_feat_size = sizeof(CXLMemSparingReadAttrs),
+ .set_feat_size = sizeof(CXLMemSparingWriteAttrs),
+ .attr_flags = CXL_FEAT_ENTRY_ATTR_FLAG_CHANGABLE |
+ CXL_FEAT_ENTRY_ATTR_FLAG_SUPPORT_DEFAULT_SEL,
+ .get_feat_version = CXL_MEMDEV_SPARING_GET_FEATURE_VERSION,
+ .set_feat_version = CXL_MEMDEV_SPARING_SET_FEATURE_VERSION,
+ .set_feat_effects = CXL_FEAT_ENTRY_SFE_IMMEDIATE_CONFIG_CHANGE |
+ CXL_FEAT_ENTRY_SFE_CEL_VALID,
+ };
+ break;
+ case CXL_FEATURE_ROW_SPARING:
+ /* Fill supported feature entry for Row Memory Sparing */
+ get_feats_out->feat_entries[entry++] =
+ (struct CXLSupportedFeatureEntry) {
+ .uuid = row_sparing_uuid,
+ .feat_index = index,
+ .get_feat_size = sizeof(CXLMemSparingReadAttrs),
+ .set_feat_size = sizeof(CXLMemSparingWriteAttrs),
+ .attr_flags = CXL_FEAT_ENTRY_ATTR_FLAG_CHANGABLE |
+ CXL_FEAT_ENTRY_ATTR_FLAG_SUPPORT_DEFAULT_SEL,
+ .get_feat_version = CXL_MEMDEV_SPARING_GET_FEATURE_VERSION,
+ .set_feat_version = CXL_MEMDEV_SPARING_SET_FEATURE_VERSION,
+ .set_feat_effects = CXL_FEAT_ENTRY_SFE_IMMEDIATE_CONFIG_CHANGE |
+ CXL_FEAT_ENTRY_SFE_CEL_VALID,
+ };
+ break;
+ case CXL_FEATURE_BANK_SPARING:
+ /* Fill supported feature entry for Bank Memory Sparing */
+ get_feats_out->feat_entries[entry++] =
+ (struct CXLSupportedFeatureEntry) {
+ .uuid = bank_sparing_uuid,
+ .feat_index = index,
+ .get_feat_size = sizeof(CXLMemSparingReadAttrs),
+ .set_feat_size = sizeof(CXLMemSparingWriteAttrs),
+ .attr_flags = CXL_FEAT_ENTRY_ATTR_FLAG_CHANGABLE |
+ CXL_FEAT_ENTRY_ATTR_FLAG_SUPPORT_DEFAULT_SEL,
+ .get_feat_version = CXL_MEMDEV_SPARING_GET_FEATURE_VERSION,
+ .set_feat_version = CXL_MEMDEV_SPARING_SET_FEATURE_VERSION,
+ .set_feat_effects = CXL_FEAT_ENTRY_SFE_IMMEDIATE_CONFIG_CHANGE |
+ CXL_FEAT_ENTRY_SFE_CEL_VALID,
+ };
+ break;
+ case CXL_FEATURE_RANK_SPARING:
+ /* Fill supported feature entry for Rank Memory Sparing */
+ get_feats_out->feat_entries[entry++] =
+ (struct CXLSupportedFeatureEntry) {
+ .uuid = rank_sparing_uuid,
+ .feat_index = index,
+ .get_feat_size = sizeof(CXLMemSparingReadAttrs),
+ .set_feat_size = sizeof(CXLMemSparingWriteAttrs),
+ .attr_flags = CXL_FEAT_ENTRY_ATTR_FLAG_CHANGABLE |
+ CXL_FEAT_ENTRY_ATTR_FLAG_SUPPORT_DEFAULT_SEL,
+ .get_feat_version = CXL_MEMDEV_SPARING_GET_FEATURE_VERSION,
+ .set_feat_version = CXL_MEMDEV_SPARING_SET_FEATURE_VERSION,
+ .set_feat_effects = CXL_FEAT_ENTRY_SFE_IMMEDIATE_CONFIG_CHANGE |
+ CXL_FEAT_ENTRY_SFE_CEL_VALID,
+ };
+ break;
default:
__builtin_unreachable();
}
@@ -1410,6 +1507,47 @@ static CXLRetCode cmd_features_get_feature(const struct cxl_cmd *cmd,
memcpy(payload_out,
(uint8_t *)&ct3d->hard_ppr_attrs + get_feature->offset,
bytes_to_copy);
+ } else if (qemu_uuid_is_equal(&get_feature->uuid,
+ &cacheline_sparing_uuid)) {
+ if (get_feature->offset >= sizeof(CXLMemSparingReadAttrs)) {
+ return CXL_MBOX_INVALID_INPUT;
+ }
+ bytes_to_copy = sizeof(CXLMemSparingReadAttrs) -
+ get_feature->offset;
+ bytes_to_copy = MIN(bytes_to_copy, get_feature->count);
+ memcpy(payload_out,
+ (uint8_t *)&ct3d->cacheline_sparing_attrs + get_feature->offset,
+ bytes_to_copy);
+ } else if (qemu_uuid_is_equal(&get_feature->uuid, &row_sparing_uuid)) {
+ if (get_feature->offset >= sizeof(CXLMemSparingReadAttrs)) {
+ return CXL_MBOX_INVALID_INPUT;
+ }
+ bytes_to_copy = sizeof(CXLMemSparingReadAttrs) -
+ get_feature->offset;
+ bytes_to_copy = MIN(bytes_to_copy, get_feature->count);
+ memcpy(payload_out,
+ (uint8_t *)&ct3d->row_sparing_attrs + get_feature->offset,
+ bytes_to_copy);
+ } else if (qemu_uuid_is_equal(&get_feature->uuid, &bank_sparing_uuid)) {
+ if (get_feature->offset >= sizeof(CXLMemSparingReadAttrs)) {
+ return CXL_MBOX_INVALID_INPUT;
+ }
+ bytes_to_copy = sizeof(CXLMemSparingReadAttrs) -
+ get_feature->offset;
+ bytes_to_copy = MIN(bytes_to_copy, get_feature->count);
+ memcpy(payload_out,
+ (uint8_t *)&ct3d->bank_sparing_attrs + get_feature->offset,
+ bytes_to_copy);
+ } else if (qemu_uuid_is_equal(&get_feature->uuid, &rank_sparing_uuid)) {
+ if (get_feature->offset >= sizeof(CXLMemSparingReadAttrs)) {
+ return CXL_MBOX_INVALID_INPUT;
+ }
+ bytes_to_copy = sizeof(CXLMemSparingReadAttrs) -
+ get_feature->offset;
+ bytes_to_copy = MIN(bytes_to_copy, get_feature->count);
+ memcpy(payload_out,
+ (uint8_t *)&ct3d->rank_sparing_attrs + get_feature->offset,
+ bytes_to_copy);
} else {
return CXL_MBOX_UNSUPPORTED;
}
@@ -1561,6 +1699,82 @@ static CXLRetCode cmd_features_set_feature(const struct cxl_cmd *cmd,
ct3d->hard_ppr_attrs.hppr_op_mode =
ct3d->hard_ppr_wr_attrs.hppr_op_mode;
}
+ } else if (qemu_uuid_is_equal(&hdr->uuid, &cacheline_sparing_uuid)) {
+ CXLMemSparingSetFeature *mem_sparing_set_feature = (void *)payload_in;
+ CXLMemSparingWriteAttrs *mem_sparing_write_attrs =
+ &mem_sparing_set_feature->feat_data;
+
+ if (hdr->version != CXL_MEMDEV_SPARING_SET_FEATURE_VERSION) {
+ return CXL_MBOX_UNSUPPORTED;
+ }
+
+ memcpy((uint8_t *)&ct3d->cacheline_sparing_wr_attrs + hdr->offset,
+ mem_sparing_write_attrs,
+ bytes_to_copy);
+ set_feat_info->data_size += bytes_to_copy;
+
+ if (data_transfer_flag == CXL_SET_FEATURE_FLAG_FULL_DATA_TRANSFER ||
+ data_transfer_flag == CXL_SET_FEATURE_FLAG_FINISH_DATA_TRANSFER) {
+ ct3d->cacheline_sparing_attrs.op_mode =
+ ct3d->cacheline_sparing_wr_attrs.op_mode;
+ }
+ } else if (qemu_uuid_is_equal(&hdr->uuid, &row_sparing_uuid)) {
+ CXLMemSparingSetFeature *mem_sparing_set_feature = (void *)payload_in;
+ CXLMemSparingWriteAttrs *mem_sparing_write_attrs =
+ &mem_sparing_set_feature->feat_data;
+
+ if (hdr->version != CXL_MEMDEV_SPARING_SET_FEATURE_VERSION) {
+ return CXL_MBOX_UNSUPPORTED;
+ }
+
+ memcpy((uint8_t *)&ct3d->row_sparing_wr_attrs + hdr->offset,
+ mem_sparing_write_attrs,
+ bytes_to_copy);
+ set_feat_info->data_size += bytes_to_copy;
+
+ if (data_transfer_flag == CXL_SET_FEATURE_FLAG_FULL_DATA_TRANSFER ||
+ data_transfer_flag == CXL_SET_FEATURE_FLAG_FINISH_DATA_TRANSFER) {
+ ct3d->row_sparing_attrs.op_mode =
+ ct3d->row_sparing_wr_attrs.op_mode;
+ }
+ } else if (qemu_uuid_is_equal(&hdr->uuid, &bank_sparing_uuid)) {
+ CXLMemSparingSetFeature *mem_sparing_set_feature = (void *)payload_in;
+ CXLMemSparingWriteAttrs *mem_sparing_write_attrs =
+ &mem_sparing_set_feature->feat_data;
+
+ if (hdr->version != CXL_MEMDEV_SPARING_SET_FEATURE_VERSION) {
+ return CXL_MBOX_UNSUPPORTED;
+ }
+
+ memcpy((uint8_t *)&ct3d->bank_sparing_wr_attrs + hdr->offset,
+ mem_sparing_write_attrs,
+ bytes_to_copy);
+ set_feat_info->data_size += bytes_to_copy;
+
+ if (data_transfer_flag == CXL_SET_FEATURE_FLAG_FULL_DATA_TRANSFER ||
+ data_transfer_flag == CXL_SET_FEATURE_FLAG_FINISH_DATA_TRANSFER) {
+ ct3d->bank_sparing_attrs.op_mode =
+ ct3d->bank_sparing_wr_attrs.op_mode;
+ }
+ } else if (qemu_uuid_is_equal(&hdr->uuid, &rank_sparing_uuid)) {
+ CXLMemSparingSetFeature *mem_sparing_set_feature = (void *)payload_in;
+ CXLMemSparingWriteAttrs *mem_sparing_write_attrs =
+ &mem_sparing_set_feature->feat_data;
+
+ if (hdr->version != CXL_MEMDEV_SPARING_SET_FEATURE_VERSION) {
+ return CXL_MBOX_UNSUPPORTED;
+ }
+
+ memcpy((uint8_t *)&ct3d->rank_sparing_wr_attrs + hdr->offset,
+ mem_sparing_write_attrs,
+ bytes_to_copy);
+ set_feat_info->data_size += bytes_to_copy;
+
+ if (data_transfer_flag == CXL_SET_FEATURE_FLAG_FULL_DATA_TRANSFER ||
+ data_transfer_flag == CXL_SET_FEATURE_FLAG_FINISH_DATA_TRANSFER) {
+ ct3d->rank_sparing_attrs.op_mode =
+ ct3d->rank_sparing_wr_attrs.op_mode;
+ }
} else {
return CXL_MBOX_UNSUPPORTED;
}
@@ -1577,6 +1791,15 @@ static CXLRetCode cmd_features_set_feature(const struct cxl_cmd *cmd,
memset(&ct3d->soft_ppr_wr_attrs, 0, set_feat_info->data_size);
} else if (qemu_uuid_is_equal(&hdr->uuid, &hard_ppr_uuid)) {
memset(&ct3d->hard_ppr_wr_attrs, 0, set_feat_info->data_size);
+ } else if (qemu_uuid_is_equal(&hdr->uuid, &cacheline_sparing_uuid)) {
+ memset(&ct3d->cacheline_sparing_wr_attrs, 0,
+ set_feat_info->data_size);
+ } else if (qemu_uuid_is_equal(&hdr->uuid, &row_sparing_uuid)) {
+ memset(&ct3d->row_sparing_wr_attrs, 0, set_feat_info->data_size);
+ } else if (qemu_uuid_is_equal(&hdr->uuid, &bank_sparing_uuid)) {
+ memset(&ct3d->bank_sparing_wr_attrs, 0, set_feat_info->data_size);
+ } else if (qemu_uuid_is_equal(&hdr->uuid, &rank_sparing_uuid)) {
+ memset(&ct3d->rank_sparing_wr_attrs, 0, set_feat_info->data_size);
}
set_feat_info->data_transfer_flag = 0;
set_feat_info->data_saved_across_reset = false;
@@ -1587,8 +1810,26 @@ static CXLRetCode cmd_features_set_feature(const struct cxl_cmd *cmd,
return CXL_MBOX_SUCCESS;
}
+#define CXL_MEM_SPARING_FLAGS_QUERY_RESOURCES BIT(0)
+#define CXL_MEM_SPARING_FLAGS_HARD_SPARING BIT(1)
+#define CXL_MEM_SPARING_FLAGS_SUB_CHANNEL_VALID BIT(2)
+#define CXL_MEM_SPARING_FLAGS_NIB_MASK_VALID BIT(3)
+
+typedef struct CXLMemSparingMaintInPayload {
+ uint8_t flags;
+ uint8_t channel;
+ uint8_t rank;
+ uint8_t nibble_mask[3];
+ uint8_t bank_group;
+ uint8_t bank;
+ uint8_t row[3];
+ uint16_t column;
+ uint8_t sub_channel;
+} QEMU_PACKED CXLMemSparingMaintInPayload;
+
static void cxl_mbox_create_mem_sparing_event_records(CXLType3Dev *ct3d,
- uint8_t class, uint8_t sub_class)
+ uint8_t class, uint8_t sub_class,
+ CXLMemSparingMaintInPayload *mem_sparing_pi)
{
CXLEventSparing event_rec = {};
@@ -1599,26 +1840,53 @@ static void cxl_mbox_create_mem_sparing_event_records(CXLType3Dev *ct3d,
cxl_device_get_timestamp(&ct3d->cxl_dstate),
1, class, 1, sub_class, 0, 0, 0, 0);
- event_rec.flags = 0;
- event_rec.result = 0;
- event_rec.validity_flags = CXL_MSER_VALID_CHANNEL |
- CXL_MSER_VALID_RANK |
- CXL_MSER_VALID_NIB_MASK |
- CXL_MSER_VALID_BANK_GROUP |
- CXL_MSER_VALID_BANK |
- CXL_MSER_VALID_ROW |
- CXL_MSER_VALID_COLUMN |
- CXL_MSER_VALID_SUB_CHANNEL;
-
- event_rec.res_avail = 1;
- event_rec.channel = 2;
- event_rec.rank = 5;
- st24_le_p(event_rec.nibble_mask, 0xA59C);
- event_rec.bank_group = 2;
- event_rec.bank = 4;
- st24_le_p(event_rec.row, 13);
- event_rec.column = 23;
- event_rec.sub_channel = 7;
+ if (mem_sparing_pi) {
+ event_rec.flags = CXL_MSER_FLAGS_QUERY_RESOURCES;
+ event_rec.result = 0;
+ event_rec.validity_flags = CXL_MSER_VALID_CHANNEL |
+ CXL_MSER_VALID_RANK |
+ CXL_MSER_VALID_NIB_MASK |
+ CXL_MSER_VALID_BANK_GROUP |
+ CXL_MSER_VALID_BANK |
+ CXL_MSER_VALID_ROW |
+ CXL_MSER_VALID_COLUMN;
+ event_rec.res_avail = 2;
+ event_rec.channel = mem_sparing_pi->channel;
+ event_rec.rank = mem_sparing_pi->rank;
+ if (mem_sparing_pi->flags & CXL_MEM_SPARING_FLAGS_NIB_MASK_VALID) {
+ __builtin_memcpy(event_rec.nibble_mask, mem_sparing_pi->nibble_mask,
+ sizeof(uint32_t));
+ }
+ event_rec.bank_group = mem_sparing_pi->bank_group;
+ event_rec.bank = mem_sparing_pi->bank;
+ event_rec.column = mem_sparing_pi->column;
+ __builtin_memcpy(event_rec.row, mem_sparing_pi->row, sizeof(uint32_t));
+ if (mem_sparing_pi->flags & CXL_MEM_SPARING_FLAGS_SUB_CHANNEL_VALID) {
+ event_rec.sub_channel = mem_sparing_pi->sub_channel;
+ event_rec.validity_flags |= CXL_MSER_VALID_SUB_CHANNEL;
+ }
+ } else {
+ event_rec.flags = 0;
+ event_rec.result = 0;
+ event_rec.validity_flags = CXL_MSER_VALID_CHANNEL |
+ CXL_MSER_VALID_RANK |
+ CXL_MSER_VALID_NIB_MASK |
+ CXL_MSER_VALID_BANK_GROUP |
+ CXL_MSER_VALID_BANK |
+ CXL_MSER_VALID_ROW |
+ CXL_MSER_VALID_COLUMN |
+ CXL_MSER_VALID_SUB_CHANNEL;
+
+ event_rec.res_avail = 1;
+ event_rec.channel = 2;
+ event_rec.rank = 5;
+ st24_le_p(event_rec.nibble_mask, 0xA59C);
+ event_rec.bank_group = 2;
+ event_rec.bank = 4;
+ st24_le_p(event_rec.row, 13);
+ event_rec.column = 23;
+ event_rec.sub_channel = 7;
+ }
if (cxl_event_insert(&ct3d->cxl_dstate,
CXL_EVENT_TYPE_INFO,
@@ -1627,6 +1895,26 @@ static void cxl_mbox_create_mem_sparing_event_records(CXLType3Dev *ct3d,
}
}
+static CXLRetCode cxl_perform_mem_sparing(CXLType3Dev *ct3d, uint8_t sub_class,
+ void *maint_pi)
+{
+ switch (sub_class) {
+ case CXL_MEMDEV_MAINT_SUBCLASS_CACHELINE_SPARING:
+ qemu_log("Cacheline Memory Sparing\n");
+ return CXL_MBOX_SUCCESS;
+ case CXL_MEMDEV_MAINT_SUBCLASS_ROW_SPARING:
+ qemu_log("Row Memory Sparing\n");
+ return CXL_MBOX_SUCCESS;
+ case CXL_MEMDEV_MAINT_SUBCLASS_BANK_SPARING:
+ qemu_log("Bank Memory Sparing\n");
+ return CXL_MBOX_SUCCESS;
+ case CXL_MEMDEV_MAINT_SUBCLASS_RANK_SPARING:
+ qemu_log("Rank Memory Sparing\n");
+ return CXL_MBOX_SUCCESS;
+ default:
+ return CXL_MBOX_INVALID_INPUT;
+ }
+}
static void cxl_perform_ppr(CXLType3Dev *ct3d, uint64_t dpa)
{
@@ -1645,7 +1933,8 @@ static void cxl_perform_ppr(CXLType3Dev *ct3d, uint64_t dpa)
CXL_MEMDEV_SPPR_OP_MODE_MEM_SPARING_EV_REC_EN) {
cxl_mbox_create_mem_sparing_event_records(ct3d,
CXL_MEMDEV_MAINT_CLASS_SPARING,
- CXL_MEMDEV_MAINT_SUBCLASS_CACHELINE_SPARING);
+ CXL_MEMDEV_MAINT_SUBCLASS_CACHELINE_SPARING,
+ NULL);
}
}
@@ -1666,6 +1955,7 @@ static CXLRetCode cmd_media_perform_maintenance(const struct cxl_cmd *cmd,
uint64_t dpa;
uint8_t nibble_mask[3];
} QEMU_PACKED ppr;
+ CXLMemSparingMaintInPayload mem_sparing_pi;
};
} QEMU_PACKED *maint_in = (void *)payload_in;
CXLType3Dev *ct3d = CXL_TYPE3(cci->d);
@@ -1691,6 +1981,32 @@ static CXLRetCode cmd_media_perform_maintenance(const struct cxl_cmd *cmd,
return CXL_MBOX_INVALID_INPUT;
}
break;
+ case CXL_MEMDEV_MAINT_CLASS_SPARING:
+ if (maint_in->mem_sparing_pi.flags &
+ CXL_MEM_SPARING_FLAGS_QUERY_RESOURCES) {
+ /*
+ * CXL r3.2 sect 8.2.10.7.1.4 - Memory Sparing Maintenance Operation
+ * Produce Memory Sparing Event record to report resources
+ * availability.
+ */
+ cxl_mbox_create_mem_sparing_event_records(ct3d, maint_in->class,
+ maint_in->subclass,
+ &maint_in->mem_sparing_pi);
+
+ return CXL_MBOX_SUCCESS;
+ }
+
+ switch (maint_in->subclass) {
+ case CXL_MEMDEV_MAINT_SUBCLASS_CACHELINE_SPARING:
+ case CXL_MEMDEV_MAINT_SUBCLASS_ROW_SPARING:
+ case CXL_MEMDEV_MAINT_SUBCLASS_BANK_SPARING:
+ case CXL_MEMDEV_MAINT_SUBCLASS_RANK_SPARING:
+ return cxl_perform_mem_sparing(ct3d, maint_in->subclass,
+ &maint_in->mem_sparing_pi);
+ default:
+ return CXL_MBOX_INVALID_INPUT;
+ }
+ break;
default:
return CXL_MBOX_INVALID_INPUT;
}
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index cf166ea05e..190fd8cd44 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -990,6 +990,50 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
.hppr_op_mode = CXL_MEMDEV_HPPR_OP_MODE_MEM_SPARING_EV_REC_EN
};
+ /* Set default value for Cacheline Memory Sparing attributes */
+ ct3d->cacheline_sparing_attrs = (CXLMemSparingReadAttrs) {
+ .max_maint_latency = 0x5, /* 100 ms */
+ .op_caps = 0, /* require host involvement */
+ .op_mode = 0,
+ .maint_op_class = CXL_MEMDEV_MAINT_CLASS_SPARING,
+ .maint_op_subclass = CXL_MEMDEV_MAINT_SUBCLASS_CACHELINE_SPARING,
+ .restriction_flags = CXL_MEMDEV_HARD_SPARING_SUPPORT_FLAG |
+ CXL_MEMDEV_SOFT_SPARING_SUPPORT_FLAG,
+ };
+
+ /* Set default value for Row Memory Sparing attributes */
+ ct3d->row_sparing_attrs = (CXLMemSparingReadAttrs) {
+ .max_maint_latency = 0x5, /* 100 ms */
+ .op_caps = 0, /* require host involvement */
+ .op_mode = 0,
+ .maint_op_class = CXL_MEMDEV_MAINT_CLASS_SPARING,
+ .maint_op_subclass = CXL_MEMDEV_MAINT_SUBCLASS_ROW_SPARING,
+ .restriction_flags = CXL_MEMDEV_HARD_SPARING_SUPPORT_FLAG |
+ CXL_MEMDEV_SOFT_SPARING_SUPPORT_FLAG,
+ };
+
+ /* Set default value for Bank Memory Sparing attributes */
+ ct3d->bank_sparing_attrs = (CXLMemSparingReadAttrs) {
+ .max_maint_latency = 0x5, /* 100 ms */
+ .op_caps = 0, /* require host involvement */
+ .op_mode = 0,
+ .maint_op_class = CXL_MEMDEV_MAINT_CLASS_SPARING,
+ .maint_op_subclass = CXL_MEMDEV_MAINT_SUBCLASS_BANK_SPARING,
+ .restriction_flags = CXL_MEMDEV_HARD_SPARING_SUPPORT_FLAG |
+ CXL_MEMDEV_SOFT_SPARING_SUPPORT_FLAG,
+ };
+
+ /* Set default value for Rank Memory Sparing attributes */
+ ct3d->rank_sparing_attrs = (CXLMemSparingReadAttrs) {
+ .max_maint_latency = 0x5, /* 100 ms */
+ .op_caps = 0, /* require host involvement */
+ .op_mode = 0,
+ .maint_op_class = CXL_MEMDEV_MAINT_CLASS_SPARING,
+ .maint_op_subclass = CXL_MEMDEV_MAINT_SUBCLASS_RANK_SPARING,
+ .restriction_flags = CXL_MEMDEV_HARD_SPARING_SUPPORT_FLAG |
+ CXL_MEMDEV_SOFT_SPARING_SUPPORT_FLAG,
+ };
+
return;
err_release_cdat:
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 947288bf0a..b337a862ce 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -598,6 +598,30 @@ typedef struct CXLMemECSWriteAttrs {
CXLMemECSFRUWriteAttrs fru_attrs[CXL_ECS_NUM_MEDIA_FRUS];
} QEMU_PACKED CXLMemECSWriteAttrs;
+/*
+ * CXL r3.2 section 8.2.10.7.2.3, Table 8-134 and 8-135:
+ * Memory Sparing Feature Readable/Writable Attributes
+ */
+typedef struct CXLMemSparingReadAttrs {
+ uint8_t max_maint_latency;
+ uint16_t op_caps;
+ uint16_t op_mode;
+ uint8_t maint_op_class;
+ uint8_t maint_op_subclass;
+ uint8_t rsvd[10];
+ uint16_t restriction_flags;
+} QEMU_PACKED CXLMemSparingReadAttrs;
+
+typedef struct CXLMemSparingWriteAttrs {
+ uint16_t op_mode;
+} QEMU_PACKED CXLMemSparingWriteAttrs;
+
+#define CXL_MEMDEV_SPARING_GET_FEATURE_VERSION 0x01
+#define CXL_MEMDEV_SPARING_SET_FEATURE_VERSION 0x01
+#define CXL_MEMDEV_SPARING_SAFE_IN_USE_FLAG BIT(0)
+#define CXL_MEMDEV_HARD_SPARING_SUPPORT_FLAG BIT(1)
+#define CXL_MEMDEV_SOFT_SPARING_SUPPORT_FLAG BIT(2)
+
#define DCD_MAX_NUM_REGION 8
typedef struct CXLDCExtentRaw {
@@ -725,6 +749,15 @@ struct CXLType3Dev {
/* ECS control attributes */
CXLMemECSReadAttrs ecs_attrs;
CXLMemECSWriteAttrs ecs_wr_attrs;
+ /* Memory Sparing control attributes */
+ CXLMemSparingReadAttrs cacheline_sparing_attrs;
+ CXLMemSparingWriteAttrs cacheline_sparing_wr_attrs;
+ CXLMemSparingReadAttrs row_sparing_attrs;
+ CXLMemSparingWriteAttrs row_sparing_wr_attrs;
+ CXLMemSparingReadAttrs bank_sparing_attrs;
+ CXLMemSparingWriteAttrs bank_sparing_wr_attrs;
+ CXLMemSparingReadAttrs rank_sparing_attrs;
+ CXLMemSparingWriteAttrs rank_sparing_wr_attrs;
struct dynamic_capacity {
HostMemoryBackend *host_dc;
diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h
index 3052bc9f18..89f6aad531 100644
--- a/include/hw/cxl/cxl_events.h
+++ b/include/hw/cxl/cxl_events.h
@@ -223,6 +223,11 @@ typedef enum CXLDCEventType {
* CXL r3.2 section Table 8-60: Memory Sparing Event Record
* All fields little endian.
*/
+
+#define CXL_MSER_FLAGS_QUERY_RESOURCES BIT(0)
+#define CXL_MSER_FLAGS_HARD_SPARING BIT(1)
+#define CXL_MSER_FLAGS_DEV_INITIATED BIT(2)
+
#define CXL_MSER_VALID_CHANNEL BIT(0)
#define CXL_MSER_VALID_RANK BIT(1)
#define CXL_MSER_VALID_NIB_MASK BIT(2)
--
2.43.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH qemu v4 7/7] hw/cxl: Add emulation for memory sparing control feature
2025-07-21 17:22 ` [PATCH qemu v4 7/7] hw/cxl: Add emulation for memory sparing control feature shiju.jose
@ 2025-07-25 13:31 ` Jonathan Cameron
0 siblings, 0 replies; 17+ messages in thread
From: Jonathan Cameron @ 2025-07-25 13:31 UTC (permalink / raw)
To: shiju.jose; +Cc: qemu-devel, linux-cxl, fan.ni, dave, linuxarm
On Mon, 21 Jul 2025 18:22:28 +0100
<shiju.jose@huawei.com> wrote:
> From: Shiju Jose <shiju.jose@huawei.com>
>
> Memory sparing is defined as a repair function that replaces a portion of
> memory with a portion of functional memory at that same DPA. The
> subclasses for this operation vary in terms of the scope of the sparing
> being performed. The Cacheline sparing subclass refers to a sparing
> action that can replace a full cacheline. Row sparing is provided as an
> alternative to PPR sparing functions and its scope is that of a single
> DDR row. Bank sparing allows an entire bank to be replaced. Rank sparing
> is defined as an operation in which an entire DDR rank is replaced.
>
> Memory sparing maintenance operations may be supported by CXL devices
> that implement CXL.mem protocol. A sparing maintenance operation requests
> the CXL device to perform a repair operation on its media.
> For example, a CXL device with DRAM components that support memory sparing
> features may implement sparing Maintenance operations.
>
> The host may issue a query command by setting Query Resources flag in the
> Input Payload (CXL Spec 3.2 Table 8-120) to determine availability of
> sparing resources for a given address. In response to a query request,
> the device shall report the resource availability by producing the Memory
> Sparing Event Record (CXL Spec 3.2 Table 8-60) in which the Channel, Rank,
> Nibble Mask, Bank Group, Bank, Row, Column, Sub-Channel fields are a copy
> of the values specified in the request.
>
> During the execution of a sparing maintenance operation, a CXL memory
> device:
> - May or may not retain data
> - May or may not be able to process CXL.mem requests correctly.
> These CXL memory device capabilities are specified by restriction flags
> in the memory sparing feature readable attributes.
>
> When a CXL device identifies error on a memory component, the device
> may inform the host about the need for a memory sparing maintenance
> operation by using DRAM event record, where the 'maintenance needed' flag
> may set. The event record contains some of the DPA, Channel, Rank,
> Nibble Mask, Bank Group, Bank, Row, Column, Sub-Channel fields that
> should be repaired. The userspace tool requests for maintenance operation
> if the 'maintenance needed' flag set in the CXL DRAM error record.
>
> CXL spec 3.2 section 8.2.10.7.2.3 describes the memory sparing feature
> discovery and configuration.
>
> CXL spec 3.2 section 8.2.10.7.1.4 describes the device's memory sparing
> maintenance operation feature.
>
> Add emulation for CXL memory device memory sparing control feature
> and memory sparing maintenance operation command.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
> + } else if (qemu_uuid_is_equal(&hdr->uuid, &rank_sparing_uuid)) {
> + CXLMemSparingSetFeature *mem_sparing_set_feature = (void *)payload_in;
> + CXLMemSparingWriteAttrs *mem_sparing_write_attrs =
> + &mem_sparing_set_feature->feat_data;
> +
> + if (hdr->version != CXL_MEMDEV_SPARING_SET_FEATURE_VERSION) {
> + return CXL_MBOX_UNSUPPORTED;
> + }
> +
> + memcpy((uint8_t *)&ct3d->rank_sparing_wr_attrs + hdr->offset,
> + mem_sparing_write_attrs,
> + bytes_to_copy);
Trivial but no need for the wrap. There were some of these in previous patch as
well.
> + set_feat_info->data_size += bytes_to_copy;
> +
> + if (data_transfer_flag == CXL_SET_FEATURE_FLAG_FULL_DATA_TRANSFER ||
> + data_transfer_flag == CXL_SET_FEATURE_FLAG_FINISH_DATA_TRANSFER) {
> + ct3d->rank_sparing_attrs.op_mode =
> + ct3d->rank_sparing_wr_attrs.op_mode;
> + }
^ permalink raw reply [flat|nested] 17+ messages in thread