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From: "Zhijian Li (Fujitsu)" <lizhijian@fujitsu.com>
To: Dan Williams <dan.j.williams@intel.com>,
	"Huang, Ying" <ying.huang@intel.com>,
	Dave Jiang <dave.jiang@intel.com>
Cc: "linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>
Subject: Re: KASAN error when insmod cxl_test
Date: Wed, 16 Oct 2024 01:23:46 +0000	[thread overview]
Message-ID: <8e68efc0-c5fb-457b-bf9d-d59b173afd4a@fujitsu.com> (raw)
In-Reply-To: <670eaf3c9f1d8_3ee22944@dwillia2-xfh.jf.intel.com.notmuch>



On 16/10/2024 02:06, Dan Williams wrote:
> Zhijian Li (Fujitsu) wrote:
>>
>>
>> On 15/10/2024 16:39, Zhijian Li (Fujitsu) wrote:
>>>
>>> All,
>>>
>>> I encountered a panic with similar calltrace
>>>
>>> I guessed I have root cause this, it was introduced since commit
>>>
>>> commit a5ab0de0ebaa65e0a75ec0761a2745c66a9d17dc
>>> Author: Dave Jiang <dave.jiang@intel.com>
>>> Date:   Tue Sep 3 17:11:51 2024 -0700
>>>
>>>        cxl: Calculate region bandwidth of targets with shared upstream link
>>>
>>>
>>> Which calls cxl_region_shared_upstream_bandwidth_update(cxlr).
>>> However, the cxl_region_shared_upstream_bandwidth_update(cxlr) works on PCI/PCIE device only
>>> while the cxl_test was implemented by platform device.
>>>
>>> I'm cooking and testing below patch
>>
>>
>> An alternative patch with a mock,
>>
>> diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild
>> index b1256fee3567..ed9f50dee3f5 100644
>> --- a/tools/testing/cxl/Kbuild
>> +++ b/tools/testing/cxl/Kbuild
>> @@ -15,6 +15,7 @@ ldflags-y += --wrap=devm_cxl_add_rch_dport
>>    ldflags-y += --wrap=cxl_rcd_component_reg_phys
>>    ldflags-y += --wrap=cxl_endpoint_parse_cdat
>>    ldflags-y += --wrap=cxl_dport_init_ras_reporting
>> +ldflags-y += --wrap=cxl_region_shared_upstream_bandwidth_update
> 
> I prefer this mock approach, thanks for tracking that down! Feel free to
> 
>>    
>>    DRIVERS := ../../../drivers
>>    CXL_SRC := $(DRIVERS)/cxl
>> @@ -61,6 +62,7 @@ cxl_core-y += $(CXL_CORE_SRC)/pci.o
>>    cxl_core-y += $(CXL_CORE_SRC)/hdm.o
>>    cxl_core-y += $(CXL_CORE_SRC)/pmu.o
>>    cxl_core-y += $(CXL_CORE_SRC)/cdat.o
>> +cxl_core-y += mock_cdat.o
> 
> My expectation is that all CXL core mocks land in
> tools/testing/cxl/test/mock.c, other than that this looks good to me.

I tried this option, but it failed with dependency check.

$depmod -a
depmod: ERROR: Cycle detected: cxl_mock -> cxl_core -> cxl_mock
depmod: ERROR: Found 2 modules in dependency cycles!
===========================

diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild
index ed9f50dee3f5..813790d40100 100644
--- a/tools/testing/cxl/Kbuild
+++ b/tools/testing/cxl/Kbuild
@@ -62,7 +62,7 @@ cxl_core-y += $(CXL_CORE_SRC)/pci.o
  cxl_core-y += $(CXL_CORE_SRC)/hdm.o
  cxl_core-y += $(CXL_CORE_SRC)/pmu.o
  cxl_core-y += $(CXL_CORE_SRC)/cdat.o
  cxl_core-$(CONFIG_TRACING) += $(CXL_CORE_SRC)/trace.o
  cxl_core-$(CONFIG_CXL_REGION) += $(CXL_CORE_SRC)/region.o
  cxl_core-y += config_check.o
diff --git a/tools/testing/cxl/mock_cdat.c b/tools/testing/cxl/mock_cdat.c
index a48d9c549651..97beb9f107bb 100644
--- a/tools/testing/cxl/mock_cdat.c
+++ b/tools/testing/cxl/mock_cdat.c
@@ -6,4 +6,3 @@
  void __wrap_cxl_region_shared_upstream_bandwidth_update(struct cxl_region *cxlr)
  {
  }
-
diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c
index f4ce96cc11d4..4c43462c1081 100644
--- a/tools/testing/cxl/test/mock.c
+++ b/tools/testing/cxl/test/mock.c
@@ -311,6 +311,11 @@ void __wrap_cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device
  }
  EXPORT_SYMBOL_NS_GPL(__wrap_cxl_dport_init_ras_reporting, CXL);
  
+void __wrap_cxl_region_shared_upstream_bandwidth_update(struct cxl_region *cxlr)
+{
+}
+EXPORT_SYMBOL_NS_GPL(__wrap_cxl_region_shared_upstream_bandwidth_update, CXL);
+
  MODULE_LICENSE("GPL v2");
  MODULE_IMPORT_NS(ACPI);
  MODULE_IMPORT_NS(CXL);


      reply	other threads:[~2024-10-16  1:23 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-10  9:03 KASAN error when insmod cxl_test Huang, Ying
2024-10-15  2:41 ` Ira Weiny
2024-10-15  3:36 ` Dan Williams
2024-10-15  4:56   ` Huang, Ying
2024-10-15 14:34   ` Ira Weiny
2024-10-15  8:39 ` Zhijian Li (Fujitsu)
2024-10-15  9:41   ` Zhijian Li (Fujitsu)
2024-10-15 15:53     ` Ira Weiny
2024-10-15 18:06     ` Dan Williams
2024-10-16  1:23       ` Zhijian Li (Fujitsu) [this message]

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