From: "Bowman, Terry" <terry.bowman@amd.com>
To: Lukas Wunner <lukas@wunner.de>
Cc: dave@stgolabs.net, jonathan.cameron@huawei.com,
dave.jiang@intel.com, alison.schofield@intel.com,
dan.j.williams@intel.com, bhelgaas@google.com,
shiju.jose@huawei.com, ming.li@zohomail.com,
Smita.KoralahalliChannabasappa@amd.com, rrichter@amd.com,
dan.carpenter@linaro.org, PradeepVineshReddy.Kodamati@amd.com,
Benjamin.Cheatham@amd.com,
sathyanarayanan.kuppuswamy@linux.intel.com,
linux-cxl@vger.kernel.org, alucerop@amd.com, ira.weiny@intel.com,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v11 09/23] PCI/AER: Report CXL or PCIe bus error type in trace logging
Date: Wed, 10 Sep 2025 10:26:19 -0500 [thread overview]
Message-ID: <910f6bda-4f18-47a9-9150-8489685c857d@amd.com> (raw)
In-Reply-To: <aK6101l5vMZA3MUs@wunner.de>
On 8/27/2025 2:37 AM, Lukas Wunner wrote:
> On Tue, Aug 26, 2025 at 08:35:24PM -0500, Terry Bowman wrote:
>> The AER service driver and aer_event tracing currently log 'PCIe Bus Type'
>> for all errors. Update the driver and aer_event tracing to log 'CXL Bus
>> Type' for CXL device errors.
>>
>> This requires the AER can identify and distinguish between PCIe errors and
>> CXL errors.
>>
>> Introduce boolean 'is_cxl' to 'struct aer_err_info'. Add assignment in
>> aer_get_device_error_info() and pci_print_aer().
>>
>> Update the aer_event trace routine to accept a bus type string parameter.
> aer_print_error() has a pointer to the struct pci_dev and you've added
> an is_cxl bit to that struct in the preceding patch.
>
> Is there a reason why you can't just use that dev->is_cxl bit, in lieu of
> adding another is_cxl bit to struct aer_err_info?
>
> If so, please document it in a code comment or at least in the commit
> message. If there isn't, please use dev->is_cxl.
>
> Thanks,
>
> Lukas
Hi Lukas,
The addition of 'is_cxl' member to 'struct aer_err_info' was requested by Dan Williams
during v7 review:
https://lore.kernel.org/linux-cxl/67abe1903a8ed_2d1e2942f@dwillia2-xfh.jf.intel.com.notmuch/
My understanding is the change was requested to encapsulate the bus error
type with the actual AER status. This is helpful when considering the
actual device bus state can change between capturing the AER status and
handling/logging. An example is a training HW error. Caching the 'is_cxl' will allow
the drivers to properly identify the error bus type for further logging and
handling.
Hopefully Dan will add his thoughts here.
Regards,
Terry
next prev parent reply other threads:[~2025-09-10 15:26 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-27 1:35 [PATCH v11 00/23] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2025-08-27 1:35 ` [PATCH v11 01/23] cxl: Remove ifdef blocks of CONFIG_PCIEAER_CXL from core/pci.c Terry Bowman
2025-08-27 1:35 ` [PATCH v11 02/23] CXL/AER: Remove CONFIG_PCIEAER_CXL and replace with CONFIG_CXL_RAS Terry Bowman
2025-08-29 15:24 ` Jonathan Cameron
2025-08-29 18:16 ` Sathyanarayanan Kuppuswamy
2025-08-27 1:35 ` [PATCH v11 03/23] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Terry Bowman
2025-08-28 15:28 ` Dave Jiang
2025-08-27 1:35 ` [PATCH v11 04/23] cxl/pci: Remove unnecessary CXL RCH " Terry Bowman
2025-08-28 8:35 ` Alejandro Lucero Palau
2025-08-28 17:32 ` Dave Jiang
2025-08-27 1:35 ` [PATCH v11 05/23] cxl: Move CXL driver RCH error handling into CONFIG_CXL_RCH_RAS conditional block Terry Bowman
2025-08-28 8:57 ` Alejandro Lucero Palau
2025-09-10 16:43 ` Bowman, Terry
2025-08-29 15:33 ` Jonathan Cameron
2025-09-11 17:48 ` Bowman, Terry
2025-09-11 19:41 ` Dave Jiang
2025-09-15 13:32 ` Bowman, Terry
2025-08-27 1:35 ` [PATCH v11 06/23] CXL/AER: Introduce rch_aer.c into AER driver for handling CXL RCH errors Terry Bowman
2025-08-28 20:53 ` Dave Jiang
2025-08-29 8:39 ` Lukas Wunner
2025-09-10 17:01 ` Bowman, Terry
2025-09-10 17:26 ` Dave Jiang
2025-09-12 13:59 ` Bowman, Terry
2025-09-12 19:09 ` Lukas Wunner
2025-09-10 16:56 ` Bowman, Terry
2025-09-10 12:43 ` Jonathan Cameron
2025-08-27 1:35 ` [PATCH v11 07/23] CXL/PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h Terry Bowman
2025-08-27 14:51 ` Lukas Wunner
2025-08-29 15:42 ` Jonathan Cameron
2025-08-29 15:47 ` Jonathan Cameron
2025-08-28 21:07 ` Dave Jiang
2025-09-10 18:11 ` Bowman, Terry
2025-09-10 20:06 ` Dave Jiang
2025-08-27 1:35 ` [PATCH v11 08/23] PCI/CXL: Introduce pcie_is_cxl() Terry Bowman
2025-08-28 8:18 ` Alejandro Lucero Palau
2025-09-10 16:24 ` Bowman, Terry
2025-09-11 3:48 ` Lukas Wunner
2025-09-10 13:10 ` Jonathan Cameron
2025-08-27 1:35 ` [PATCH v11 09/23] PCI/AER: Report CXL or PCIe bus error type in trace logging Terry Bowman
2025-08-27 7:37 ` Lukas Wunner
2025-09-10 15:26 ` Bowman, Terry [this message]
2025-09-10 15:33 ` Lukas Wunner
2025-09-11 5:07 ` Lukas Wunner
2025-08-27 1:35 ` [PATCH v11 10/23] CXL/AER: Update PCI class code check to use FIELD_GET() Terry Bowman
2025-08-29 16:03 ` Jonathan Cameron
2025-09-11 18:18 ` Bowman, Terry
2025-08-27 1:35 ` [PATCH v11 11/23] cxl/pci: Update RAS handler interfaces to also support CXL Ports Terry Bowman
2025-08-27 1:35 ` [PATCH v11 12/23] cxl/pci: Log message if RAS registers are unmapped Terry Bowman
2025-08-27 1:35 ` [PATCH v11 13/23] cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports Terry Bowman
2025-08-27 11:55 ` Shiju Jose
2025-08-29 16:06 ` Jonathan Cameron
2025-08-27 1:35 ` [PATCH v11 14/23] cxl/pci: Update cxl_handle_cor_ras() to return early if no RAS errors Terry Bowman
2025-08-27 1:35 ` [PATCH v11 15/23] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2025-08-28 23:05 ` Dave Jiang
2025-09-10 18:40 ` Bowman, Terry
2025-08-27 1:35 ` [PATCH v11 16/23] cxl/pci: Introduce CXL Endpoint protocol error handlers Terry Bowman
2025-08-27 7:48 ` Lukas Wunner
2025-09-10 13:23 ` Jonathan Cameron
2025-08-27 1:35 ` [PATCH v11 17/23] CXL/AER: Introduce cxl_aer.c into AER driver for forwarding CXL errors Terry Bowman
2025-08-27 7:56 ` Lukas Wunner
2025-08-27 1:35 ` [PATCH v11 18/23] PCI/AER: Dequeue forwarded CXL error Terry Bowman
2025-08-29 0:43 ` Dave Jiang
2025-08-29 7:10 ` Lukas Wunner
2025-09-16 15:18 ` Bowman, Terry
2025-09-11 14:33 ` Bowman, Terry
2025-09-11 15:41 ` Dave Jiang
2025-09-11 16:47 ` Bowman, Terry
2025-09-11 19:45 ` Dave Jiang
2025-09-10 13:29 ` Jonathan Cameron
2025-08-27 1:35 ` [PATCH v11 19/23] CXL/PCI: Introduce CXL Port protocol error handlers Terry Bowman
2025-08-30 0:17 ` Dave Jiang
2025-08-27 1:35 ` [PATCH v11 20/23] CXL/PCI: Export and rename merge_result() to pci_ers_merge_result() Terry Bowman
2025-08-27 8:04 ` Lukas Wunner
2025-09-10 15:57 ` Bowman, Terry
2025-09-11 3:44 ` Lukas Wunner
2025-08-27 12:19 ` kernel test robot
2025-08-27 1:35 ` [PATCH v11 21/23] CXL/PCI: Introduce CXL uncorrectable protocol error recovery Terry Bowman
2025-09-03 22:30 ` Dave Jiang
2025-09-11 19:19 ` Bowman, Terry
2025-09-11 19:48 ` Dave Jiang
2025-09-10 13:33 ` Jonathan Cameron
2025-08-27 1:35 ` [PATCH v11 22/23] CXL/PCI: Enable CXL protocol errors during CXL Port probe Terry Bowman
2025-09-03 23:23 ` Dave Jiang
2025-08-27 1:35 ` [PATCH v11 23/23] CXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup Terry Bowman
2025-09-10 15:07 ` Gregory Price
2025-09-11 20:19 ` Bowman, Terry
2025-08-29 0:07 ` [PATCH v11 00/23] Enable CXL PCIe Port Protocol Error handling and logging Dave Jiang
2025-09-23 3:29 ` Gregory Price
2025-09-23 9:21 ` Srinivasulu Thanneeru
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