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Wed, 24 Jun 2026 09:42:58 -0700 (PDT) X-Received: by 2002:a05:7301:7106:b0:2f4:d190:37bf with SMTP id 5a478bee46e88-30c5563f2e8mr4507498eec.16.1782319378075; Wed, 24 Jun 2026 09:42:58 -0700 (PDT) Received: from [192.168.68.103] ([189.79.21.40]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30c7c8b1ae5sm400755eec.16.2026.06.24.09.42.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 24 Jun 2026 09:42:57 -0700 (PDT) Message-ID: <9279723a-b079-4749-b3a5-e6e7ecfd2121@oss.qualcomm.com> Date: Wed, 24 Jun 2026 13:42:48 -0300 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/4] hw/riscv/virt: Add CXL support to the RISC-V virt machine To: Chen Pei , jic23@kernel.org, pbonzini@redhat.com, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, sunilvl@ventanamicro.com, dave.jiang@intel.com, alison.schofield@intel.com, imammedo@redhat.com, mst@redhat.com, guoren@kernel.org Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org References: <20260618093827.3507-1-cp0613@linux.alibaba.com> <20260618093827.3507-2-cp0613@linux.alibaba.com> From: Daniel Henrique Barboza Content-Language: en-US In-Reply-To: <20260618093827.3507-2-cp0613@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI0MDE0MCBTYWx0ZWRfXxuK7k/5x6BIx G2pN5BUYAj1gxWFT8DLdx1nW1e346XtytEmAVGxsZfJh5LMXirMWQtzfXoC7npOYYpyRYAaDASa 6k7n2ctNhdJAydOcAcLgX/a9z+yh7O0= X-Proofpoint-GUID: QWbhbMe1O8rumTw56qMizp-0w-wbZjHJ X-Authority-Analysis: v=2.4 cv=Ar7eGu9P c=1 sm=1 tr=0 ts=6a3c0913 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=sHJf4AwOIoU3qjeHFPlg6Q==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=SRrdq9N9AAAA:8 a=OKAgqmDqJgUB0MQQqyQA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: QWbhbMe1O8rumTw56qMizp-0w-wbZjHJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI0MDE0MCBTYWx0ZWRfX1XbvoJ8MOrBw +yyoB233FPrIMCR+9kGlLScFYmupw1NxhG+d9XbeM/6M7uIqvMt6YgSuzB3Ri7ISBQO2J+IyHRy P6t/uPPS5FA62Oh0Fo/wUrkgppBCADpHS7BVcOzj+1CxuinCct2hC1kzFLRMveEIlpBCvlgtIY4 bHMCg7TYF1gSehOxNnDT9NaPrz5Sx7qdTk3ei2Jn9pGdzvXoygtdBdSfRY0PgVNPGU2ipcEyDhG VW1ZVBgLY7JjIUNxDMf28P1qgJMdbEkeNNtWJHaeijqYLJ0Ihiy58vU2Bm4VhHsJTW7JzJFEGx1 /GwleCgIRmoSrKAl3yxHkohDyFtXfgiipKMjoAIPQEt5EbeSFmH9zQh1QJGPZmhphBPMb/HlFBC hJS6mPUcjDkDXr53oYaExNiNwNHjWQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-24_03,2026-06-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 adultscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606240140 Hi, On 6/18/2026 6:38 AM, Chen Pei wrote: > Enable CXL support on the RISC-V virt machine following the same > approach used by the ARM virt machine: > - Add PXB and ACPI_CXL Kconfig selections > - Add CXLState and PCIBus pointer to RISCVVirtState > - Register CXL machine properties via cxl_machine_init() > - Create CXL host register region above the PCIe high MMIO region > - Call cxl_hook_up_pxb_registers() and cxl_fmws_link_targets() at > machine_done time > - Map Fixed Memory Windows above the CXL host register region > - Add ACPI0017 device in DSDT and build CEDT table in virt-acpi-build.c > > Signed-off-by: Chen Pei > --- > hw/riscv/Kconfig | 2 ++ > hw/riscv/virt-acpi-build.c | 20 +++++++++++++++++++ > hw/riscv/virt.c | 40 ++++++++++++++++++++++++++++++++++++++ > include/hw/riscv/virt.h | 3 +++ > 4 files changed, 65 insertions(+) > > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig > index 2518b04175..ebd0355f09 100644 > --- a/hw/riscv/Kconfig > +++ b/hw/riscv/Kconfig > @@ -66,8 +66,10 @@ config RISCV_VIRT > select VIRTIO_MMIO > select FW_CFG_DMA > select PLATFORM_BUS > + select PXB > select ACPI > select ACPI_PCI > + select ACPI_CXL > > config SHAKTI_C > bool > diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c > index 413d47d70e..309d64b322 100644 > --- a/hw/riscv/virt-acpi-build.c > +++ b/hw/riscv/virt-acpi-build.c > @@ -29,12 +29,16 @@ > #include "hw/acpi/aml-build.h" > #include "hw/acpi/pci.h" > #include "hw/acpi/utils.h" > +#include "hw/acpi/cxl.h" > #include "hw/intc/riscv_aclint.h" > #include "hw/nvram/fw_cfg_acpi.h" > #include "hw/pci-host/gpex.h" > +#include "hw/pci/pci_bus.h" > #include "hw/riscv/virt.h" > #include "hw/riscv/numa.h" > #include "hw/virtio/virtio-acpi.h" > +#include "hw/cxl/cxl.h" > +#include "hw/cxl/cxl_host.h" > #include "kvm/kvm_riscv.h" > #include "migration/vmstate.h" > #include "qapi/error.h" > @@ -503,6 +507,17 @@ static void build_dsdt(GArray *table_data, > acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES * 2); > } > > + if (s->cxl_devices_state.is_enabled) { > + Aml *cxl_dev = aml_device("CXLM"); > + aml_append(cxl_dev, aml_name_decl("_HID", aml_string("ACPI0017"))); > + Aml *method = aml_method("_STA", 0, AML_NOTSERIALIZED); > + aml_append(method, aml_return(aml_int(0x0B))); > + aml_append(cxl_dev, method); > + build_cxl_dsm_method(cxl_dev); > + > + aml_append(scope, cxl_dev); > + } > + > aml_append(dsdt, scope); > > /* copy AML table into ACPI tables blob and patch header there */ > @@ -910,6 +925,11 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) > s->oem_table_id); > } > > + if (s->cxl_devices_state.is_enabled) { > + cxl_build_cedt(table_offsets, tables_blob, tables->linker, > + s->oem_id, s->oem_table_id, &s->cxl_devices_state); > + } > + > if (ms->numa_state->num_nodes > 0) { > acpi_add_table(table_offsets, tables_blob); > build_srat(tables_blob, tables->linker, s); > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index ce64eaaef7..84b91b4322 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -55,6 +55,8 @@ > #include "hw/pci/pci.h" > #include "hw/pci-host/gpex.h" > #include "hw/display/ramfb.h" > +#include "hw/cxl/cxl.h" > +#include "hw/cxl/cxl_host.h" > #include "hw/acpi/aml-build.h" > #include "qapi/qapi-visit-common.h" > #include "hw/virtio/virtio-iommu.h" > @@ -1259,9 +1261,27 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, > } > > GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(dev)->bus; > + s->pci_bus = PCI_HOST_BRIDGE(dev)->bus; > return dev; > } > > +static void create_cxl_host_reg_region(RISCVVirtState *s) > +{ > + MemoryRegion *sysmem = get_system_memory(); > + MemoryRegion *mr = &s->cxl_devices_state.host_mr; > + hwaddr base; > + > + if (!s->cxl_devices_state.is_enabled) { > + return; > + } > + > + base = virt_high_pcie_memmap.base + virt_high_pcie_memmap.size; > + base = ROUND_UP(base, 64 * KiB); > + > + memory_region_init(mr, OBJECT(s), "cxl_host_reg", 64 * KiB * 16); > + memory_region_add_subregion(sysmem, base, mr); > +} > + > static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base) > { > FWCfgState *fw_cfg; > @@ -1426,6 +1446,13 @@ static void virt_machine_done(Notifier *notifier, void *data) > machine_done); > MachineState *machine = MACHINE(s); > hwaddr start_addr = s->memmap[VIRT_DRAM].base; > + > + cxl_hook_up_pxb_registers(s->pci_bus, &s->cxl_devices_state, > + &error_fatal); > + > + if (s->cxl_devices_state.is_enabled) { > + cxl_fmws_link_targets(&error_fatal); > + } > hwaddr firmware_end_addr; > vaddr kernel_start_addr; > const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); > @@ -1663,6 +1690,17 @@ static void virt_machine_init(MachineState *machine) > ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); > } > > + create_cxl_host_reg_region(s); > + > + if (s->cxl_devices_state.is_enabled) { > + hwaddr cxl_base = virt_high_pcie_memmap.base + > + virt_high_pcie_memmap.size; > + cxl_base += memory_region_size(&s->cxl_devices_state.host_mr); > + cxl_base = ROUND_UP(cxl_base, 256 * MiB); > + cxl_fmws_set_memmap(cxl_base, UINT64_MAX); > + cxl_fmws_update_mmio(); > + } > + create_cxl_host_reg_region() is doing the same check: if (!s->cxl_devices_state.is_enabled) { (...) Maybe we could squash these update_mmio() lines in the same helper to have everything CXL related in the same place. The helper would need to be renamed to something more appropriate (e.g. cxl_host_state_init() since we're at init time). Patch LGTM otherwise. Thanks, Daniel > /* register system main memory (actual RAM) */ > memory_region_add_subregion(system_memory, s->memmap[VIRT_DRAM].base, > machine->ram); > @@ -1769,6 +1807,8 @@ static void virt_machine_instance_init(Object *obj) > s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); > s->acpi = ON_OFF_AUTO_AUTO; > s->iommu_sys = ON_OFF_AUTO_AUTO; > + > + cxl_machine_init(obj, &s->cxl_devices_state); > } > > static char *virt_get_aia_guests(Object *obj, Error **errp) > diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h > index 18a2a323a3..7d559ac610 100644 > --- a/include/hw/riscv/virt.h > +++ b/include/hw/riscv/virt.h > @@ -24,6 +24,7 @@ > #include "hw/core/sysbus.h" > #include "hw/block/flash.h" > #include "hw/intc/riscv_imsic.h" > +#include "hw/cxl/cxl.h" > > #define VIRT_CPUS_MAX_BITS 9 > #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) > @@ -64,6 +65,8 @@ struct RISCVVirtState { > struct GPEXHost *gpex_host; > OnOffAuto iommu_sys; > uint16_t pci_iommu_bdf; > + CXLState cxl_devices_state; > + PCIBus *pci_bus; > }; > > enum {