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b=WR3NQSHYk8qlbjSsXN72IMUEMIK9HZnIoGTfBre9aMeIW5hZ15aiNVsjoEJWcddCuFqRHNp74BweT385pFb0Ubk3SUpz+3iiIWTErai9lNBlOdpSl8NnntpjbFpmFw13nn43aIoq0d9imcbPeL4rOg3HRt7j/5M7L0PiTsyQTf4= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from DS0PR12MB6390.namprd12.prod.outlook.com (2603:10b6:8:ce::7) by DM4PR12MB6136.namprd12.prod.outlook.com (2603:10b6:8:a9::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9094.22; Wed, 10 Sep 2025 16:24:24 +0000 Received: from DS0PR12MB6390.namprd12.prod.outlook.com ([fe80::38ec:7496:1a35:599f]) by DS0PR12MB6390.namprd12.prod.outlook.com ([fe80::38ec:7496:1a35:599f%5]) with mapi id 15.20.9094.021; Wed, 10 Sep 2025 16:24:23 +0000 Message-ID: <9714dd6a-28c1-4c2a-8558-9f3d7e3f01b0@amd.com> Date: Wed, 10 Sep 2025 11:24:20 -0500 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v11 08/23] PCI/CXL: Introduce pcie_is_cxl() To: Alejandro Lucero Palau , dave@stgolabs.net, jonathan.cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, dan.j.williams@intel.com, bhelgaas@google.com, shiju.jose@huawei.com, ming.li@zohomail.com, Smita.KoralahalliChannabasappa@amd.com, rrichter@amd.com, dan.carpenter@linaro.org, PradeepVineshReddy.Kodamati@amd.com, lukas@wunner.de, Benjamin.Cheatham@amd.com, sathyanarayanan.kuppuswamy@linux.intel.com, linux-cxl@vger.kernel.org, ira.weiny@intel.com Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <20250827013539.903682-1-terry.bowman@amd.com> <20250827013539.903682-9-terry.bowman@amd.com> <43c373b4-6ff3-418c-93a0-f679375f117e@amd.com> Content-Language: en-US From: "Bowman, Terry" In-Reply-To: <43c373b4-6ff3-418c-93a0-f679375f117e@amd.com> Content-Type: text/plain; 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The CXL Flexbus DVSEC >> presence is used because it is required for all the CXL PCIe devices.[1] >> >> Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL >> CXL.cache and CXl.mem status. >> >> In the case the device is an EP or USP, call set_pcie_cxl() on behalf of >> the parent downstream device. This will make certain the correct state >> is cached. >> >> Add function pcie_is_cxl() to return 'struct pci_dev::is_cxl'. >> >> [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended >> Capability (DVSEC) ID Assignment, Table 8-2 >> >> Signed-off-by: Terry Bowman >> Reviewed-by: Ira Weiny >> Reviewed-by: Kuppuswamy Sathyanarayanan >> Reviewed-by: Dave Jiang >> Reviewed-by: Jonathan Cameron > > With the changes for checking flexbus state: > > > Reviewed-by: Alejandro Lucero > Thanks Alejandro. > Just a minor thing below, something I do not fully understand but I > guess it was discussed/explained previously. > > >> --- >> Changes in v10->v11: >> - Amended set_pcie_cxl() to check for Upstream Port's and EP's parent >> downstream port by calling set_pcie_cxl(). (Dan) >> - Retitle patch: 'Add' -> 'Introduce' >> - Add check for CXL.mem and CXL.cache (Alejandro, Dan) >> --- >> drivers/pci/probe.c | 25 +++++++++++++++++++++++++ >> include/linux/pci.h | 6 ++++++ >> include/uapi/linux/pci_regs.h | 3 +++ >> 3 files changed, 34 insertions(+) >> >> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c >> index 4b8693ec9e4c..b08cd0346136 100644 >> --- a/drivers/pci/probe.c >> +++ b/drivers/pci/probe.c >> @@ -1691,6 +1691,29 @@ static void set_pcie_thunderbolt(struct pci_dev *dev) >> dev->is_thunderbolt = 1; >> } >> >> +static void set_pcie_cxl(struct pci_dev *dev) >> +{ >> + struct pci_dev *parent; >> + u16 dvsec = pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, >> + PCI_DVSEC_CXL_FLEXBUS_PORT); >> + if (dvsec) { >> + u16 cap; >> + >> + pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_FLEXBUS_STATUS_OFFSET, &cap); >> + >> + dev->is_cxl = FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_STATUS_CACHE_MASK, cap) || >> + FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_STATUS_MEM_MASK, cap); >> + } >> + >> + if (!pci_is_pcie(dev) || >> + !(pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT || >> + pci_pcie_type(dev) == PCI_EXP_TYPE_UPSTREAM)) >> + return; >> + >> + parent = pci_upstream_bridge(dev); >> + set_pcie_cxl(parent); > > This recursion is confusing to me. > > Is it not the parent already having this set from its own pci setup? Or > maybe do we expect that to change after a reset and this is a sanity check? > Right. The upstream parent bus state is already set but could change after reset. Terry