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Message-ID: <973576304.21789064282642.JavaMail.epsvc@epcpadp2new> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In-Reply-To: <20260830072144.399508-1-junjie.cao@intel.com> X-CMS-MailID: 20260910084057epcas5p3035baa4d94172108ad8e044c123c491c X-Msg-Generator: CA Content-Type: multipart/mixed; boundary="----SSW395WYaxe49lwLPbcWHEEKUIW3_c_Q3XTd.OaaloguMMey=_1c4db_" CMS-TYPE: 105P X-CPGSPASS: Y X-Hop-Count: 3 X-CMS-RootMailID: 20260910084057epcas5p3035baa4d94172108ad8e044c123c491c References: <1212772528.01787732282387.JavaMail.epsvc@epcpadp2new> <20260830072144.399508-1-junjie.cao@intel.com> ------SSW395WYaxe49lwLPbcWHEEKUIW3_c_Q3XTd.OaaloguMMey=_1c4db_ Content-Type: text/plain; charset="utf-8"; format="flowed" Content-Disposition: inline On 30/08/26 03:21PM, Junjie Cao wrote: >On the register defines: v1 ended with routing these through >pci_regs.h plus a note on when the kernel header picks them up; they >went into QEMU's pcie_regs.h instead. Still the plan for a later >spin, or intentional? > >Many thanks, >Junjie Hi Junjie, The register definitions are intentionally placed in QEMU's include/hw/pci/pci_regs.h for now. Once The corresponding macros are merged into Linux Kernel's include/uapi/linux/pci_regs.h, will sync them through include/standard headers/linux/pci_regs.h in a follow-up patch. Thanks and regards, Shrihari ------SSW395WYaxe49lwLPbcWHEEKUIW3_c_Q3XTd.OaaloguMMey=_1c4db_ Content-Type: text/plain; charset="utf-8" ------SSW395WYaxe49lwLPbcWHEEKUIW3_c_Q3XTd.OaaloguMMey=_1c4db_--