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X-CSE-ConnectionGUID: 9hbPp3zxQFiD82AsXvPD7g== X-CSE-MsgGUID: 40Us0iaKQsCbViqL+6iaqg== X-IronPort-AV: E=McAfee;i="6800,10657,11864"; a="85301109" X-IronPort-AV: E=Sophos;i="6.25,202,1779174000"; d="scan'208";a="85301109" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2026 11:03:27 -0700 X-CSE-ConnectionGUID: bvPtUuIrTaW08GIIo93z8Q== X-CSE-MsgGUID: 3nD+Z1FJSGCspWyysoSRTA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,202,1779174000"; d="scan'208";a="299505437" Received: from bradocaj-mobl.ger.corp.intel.com (HELO [10.125.108.187]) ([10.125.108.187]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2026 11:03:25 -0700 Message-ID: <9b3a1271-642f-442d-b545-d00d6863a54c@intel.com> Date: Mon, 3 Aug 2026 11:03:24 -0700 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v12 1/8] cxl/mbox: Flag support for Dynamic Capacity Devices (DCD) To: Anisa Su , linux-cxl@vger.kernel.org Cc: nvdimm@lists.linux.dev, linux-kernel@vger.kernel.org, Alison Schofield , Jonathan Cameron , Fan Ni , Li Ming , Vishal Verma , Davidlohr Bueso , Ira Weiny , Benjamin Cheatham , Wonjae Lee , Junhee Park , Heesoo Kim , Anisa Su References: <20260731084901.1512819-1-anisa.su@samsung.com> <20260731084901.1512819-2-anisa.su@samsung.com> From: Dave Jiang Content-Language: en-US In-Reply-To: <20260731084901.1512819-2-anisa.su@samsung.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 7/31/26 1:48 AM, Anisa Su wrote: > From: Ira Weiny > > Per the CXL 4.0 specification software must check the Command Effects > Log (CEL) for dynamic capacity command support. > > Detect support for the DCD commands while reading the CEL, including: > > Get DC Config > Get DC Extent List > Add DC Response > Release DC > > Based on an original patch by Navneet Singh. > > Signed-off-by: Ira Weiny > Signed-off-by: Anisa Su > Tested-by: Wonjae Lee > Tested-by: Junhee Park > Tested-by: Heesoo Kim > > --- > Changes: > 1. mbox.c: leave mds->dcd_supported false so the hardware enablement > patches can be upstreamed ahead of the extent and DAX work; the > event handling patch re-enables it. > --- > drivers/cxl/core/mbox.c | 44 +++++++++++++++++++++++++++++++++++++++++ > drivers/cxl/cxlmem.h | 20 +++++++++++++++++++ > 2 files changed, 64 insertions(+) > > diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c > index 7c6c5b7450a5..4790524c32a7 100644 > --- a/drivers/cxl/core/mbox.c > +++ b/drivers/cxl/core/mbox.c > @@ -165,6 +165,38 @@ static void cxl_set_security_cmd_enabled(struct cxl_security_state *security, > } > } > > +static bool cxl_is_dcd_command(u16 opcode) > +{ > +#define CXL_MBOX_OP_DCD_CMDS 0x48 > + > + return (opcode >> 8) == CXL_MBOX_OP_DCD_CMDS; > +} > + > +static void cxl_set_dcd_cmd_enabled(u16 opcode, unsigned long *cmd_mask) > +{ > + switch (opcode) { > + case CXL_MBOX_OP_GET_DC_CONFIG: > + set_bit(CXL_DCD_ENABLED_GET_CONFIG, cmd_mask); > + break; > + case CXL_MBOX_OP_GET_DC_EXTENT_LIST: > + set_bit(CXL_DCD_ENABLED_GET_EXTENT_LIST, cmd_mask); > + break; > + case CXL_MBOX_OP_ADD_DC_RESPONSE: > + set_bit(CXL_DCD_ENABLED_ADD_RESPONSE, cmd_mask); > + break; > + case CXL_MBOX_OP_RELEASE_DC: > + set_bit(CXL_DCD_ENABLED_RELEASE, cmd_mask); > + break; > + default: > + break; > + } > +} > + > +static bool cxl_verify_dcd_cmds(unsigned long *cmds_seen) > +{ > + return bitmap_full(cmds_seen, CXL_DCD_ENABLED_MAX); > +} > + > static bool cxl_is_poison_command(u16 opcode) > { > #define CXL_MBOX_OP_POISON_CMDS 0x43 > @@ -757,6 +789,7 @@ static void cxl_walk_cel(struct cxl_memdev_state *mds, size_t size, u8 *cel) > struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox; > struct cxl_cel_entry *cel_entry; > const int cel_entries = size / sizeof(*cel_entry); > + DECLARE_BITMAP(dcd_cmds, CXL_DCD_ENABLED_MAX) = {}; > struct device *dev = mds->cxlds.dev; > int i, ro_cmds = 0, wr_cmds = 0; > > @@ -785,11 +818,22 @@ static void cxl_walk_cel(struct cxl_memdev_state *mds, size_t size, u8 *cel) > enabled++; > } > > + if (cxl_is_dcd_command(opcode)) { > + cxl_set_dcd_cmd_enabled(opcode, dcd_cmds); > + enabled++; > + } > + > dev_dbg(dev, "Opcode 0x%04x %s\n", opcode, > enabled ? "enabled" : "unsupported by driver"); > } > > set_features_cap(cxl_mbox, ro_cmds, wr_cmds); > + /* > + * Disabled until event handling implemented. > + */ > + if (cxl_verify_dcd_cmds(dcd_cmds)) > + dev_dbg(dev, "Device supports DCD; capability disabled\n"); > + mds->dcd_supported = false; Assume this is intentional to disable DCD for the prep series. Should mention that in the commit log as something to come back to and change later. Also prevent sashiko from tripping on that. With the note: Reviewed-by: Dave Jiang DJ > } > > static struct cxl_mbox_get_supported_logs *cxl_get_gsl(struct cxl_memdev_state *mds) > diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h > index ed419d0c59f2..616eeaeee5b9 100644 > --- a/drivers/cxl/cxlmem.h > +++ b/drivers/cxl/cxlmem.h > @@ -252,6 +252,20 @@ struct cxl_event_state { > struct mutex log_lock; > }; > > +/** > + * CXL r4.0 Section 8.2.10.9 - Memory Device Command Sets. See Table 8-308. > + * > + * The 48h Command Set (Opcodes 4800h - 4803h) defines the device-enabled DCD > + * commands. > + */ > +enum dcd_cmd_enabled_bits { > + CXL_DCD_ENABLED_GET_CONFIG, > + CXL_DCD_ENABLED_GET_EXTENT_LIST, > + CXL_DCD_ENABLED_ADD_RESPONSE, > + CXL_DCD_ENABLED_RELEASE, > + CXL_DCD_ENABLED_MAX > +}; > + > /* Device enabled poison commands */ > enum poison_cmd_enabled_bits { > CXL_POISON_ENABLED_LIST, > @@ -427,6 +441,7 @@ static inline struct cxl_dev_state *mbox_to_cxlds(struct cxl_mailbox *cxl_mbox) > * @partition_align_bytes: alignment size for partition-able capacity > * @active_volatile_bytes: sum of hard + soft volatile > * @active_persistent_bytes: sum of hard + soft persistent > + * @dcd_supported: all DCD commands are supported > * @event: event log driver state > * @poison: poison driver state info > * @security: security driver state info > @@ -446,6 +461,7 @@ struct cxl_memdev_state { > u64 partition_align_bytes; > u64 active_volatile_bytes; > u64 active_persistent_bytes; > + bool dcd_supported; > > struct cxl_event_state event; > struct cxl_poison_state poison; > @@ -507,6 +523,10 @@ enum cxl_opcode { > CXL_MBOX_OP_UNLOCK = 0x4503, > CXL_MBOX_OP_FREEZE_SECURITY = 0x4504, > CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505, > + CXL_MBOX_OP_GET_DC_CONFIG = 0x4800, > + CXL_MBOX_OP_GET_DC_EXTENT_LIST = 0x4801, > + CXL_MBOX_OP_ADD_DC_RESPONSE = 0x4802, > + CXL_MBOX_OP_RELEASE_DC = 0x4803, > CXL_MBOX_OP_MAX = 0x10000 > }; >