From: Dave Jiang <dave.jiang@intel.com>
To: Linus Torvalds <torvalds@linux-foundation.org>
Cc: "linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>
Subject: [GIT PULL] Compute Express Link (CXL) for 6.12
Date: Fri, 27 Sep 2024 07:02:57 -0700 [thread overview]
Message-ID: <9c4d4de9-5c24-4644-ba41-875bf19da10b@intel.com> (raw)
Hi Linus, please pull from:
git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git cxl-for-6.12
...to receive updates for CXL subsystem.
Changes contain a patch series to address HDM decoder initialization from DVSEC
ranges, a patch series that refactors the code related to cxl mailboxes to be
independent of the memory devices, a patch series that adds support for shared
upstream link access_coordinate calculation, as well as a change to remove
locking from memory notifier callback. In addition, a number of misc cleanups
and refactoring of the code are also included.
These have all appeared in -next for a few days with no reported issues.
---
The following changes since commit 431c1646e1f86b949fa3685efc50b660a364c2b6:
Linux 6.11-rc6 (2024-09-01 19:46:02 +1200)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git cxl-for-6.12
for you to fetch changes up to 2c70677dabb5e326467160e28915b804b925b53b:
cxl: Add documentation to explain the shared link bandwidth calculation (2024-09-22 21:29:08 -0700)
----------------------------------------------------------------
cxl changes for v6.12
Misc cleanups:
- Convert devm_cxl_add_root() to return using ERR_CAST().
- cxl_test use dev_is_platform() instead of open coding.
- Remove duplicate include of header core.h in core/cdat.c.
- use scoped resource management to drop put_device() for cxl_port
- Use scoped_guard to drop device_lock() for cxl_port
- Refactor __devm_cxl_add_port() to drop gotos
- Rename cxl_setup_parent_dport to cxl_dport_init_aer and cxl_dport_map_regs()
to cxl_dport_map_ras().
- Refactor cxl_dport_init_aer() to be more concise.
- Remove duplicate host_bridge->native_aer checking in cxl_dport_init_ras_reporting().
- Fix comment for cxl_query_cmd()
Series to address HDM decoder initialization from DVSEC ranges:
- Only register non-zero DVSEC ranges.
- Remove duplicate implementation of waiting for memory_info_valid.
- Simplify the checking of mem_enabled in cxl_hdm_decode_init().
Remove locking from memory notifier callback
Series that refactors the code related to cxl mailboxes to be independent of the memory devices
- Move cxl headers in include/linux/ to include/cxl.
- Move all mailbox related data to 'struct cxl_mailbox'.
- Refactor mailbox APIs with 'struct cxl_mailbox' as input instead of memory device state.
Series that adds support for shared upstream link access_coordinate calculation for
configurations that have multiple targets under a switch or a root port where the
aggregated bandwidth can be greater than the upstream link of the switch/RP upstream
link.
- Preserve the CDAT access_coordinate from an endpoint
- Add the support for shared upstream link access_coordinate calculation
- Add documentation to explain how the calculations are done.
----------------------------------------------------------------
Dave Jiang (7):
cxl: move cxl headers to new include/cxl/ directory
cxl: Move mailbox related bits to the same context
cxl: Convert cxl_internal_send_cmd() to use 'struct cxl_mailbox' as input
cxl: Fix comment regarding cxl_query_cmd() return data
cxl: Preserve the CDAT access_coordinate for an endpoint
cxl: Calculate region bandwidth of targets with shared upstream link
cxl: Add documentation to explain the shared link bandwidth calculation
Hongbo Li (1):
cxl: Remove duplicate included header file core.h
Ira Weiny (1):
cxl/region: Remove lock from memory notifier callback
Kunwu Chan (1):
tools/testing/cxl: Use dev_is_platform()
Li Ming (6):
cxl/port: Use __free() to drop put_device() for cxl_port
cxl/port: Use scoped_guard()/guard() to drop device_lock() for cxl_port
cxl/port: Refactor __devm_cxl_add_port() to drop goto pattern
cxl/pci: Rename cxl_setup_parent_dport() and cxl_dport_map_regs()
cxl/pci: cxl_dport_map_rch_aer() cleanup
cxl/pci: Remove duplicate host_bridge->native_aer checking
Yanfei Xu (4):
cxl/pci: Fix to record only non-zero ranges
cxl/pci: Remove duplicated implementation of waiting for memory_info_valid
cxl/pci: Check Mem_info_valid bit for each applicable DVSEC
cxl/pci: simplify the check of mem_enabled in cxl_hdm_decode_init()
Yuesong Li (1):
cxl/port: Convert to use ERR_CAST()
.../driver-api/cxl/access-coordinates.rst | 91 ++++
Documentation/driver-api/cxl/index.rst | 1 +
MAINTAINERS | 3 +-
drivers/acpi/apei/einj-cxl.c | 2 +-
drivers/acpi/apei/ghes.c | 2 +-
drivers/cxl/core/cdat.c | 508 ++++++++++++++++++++-
drivers/cxl/core/core.h | 4 +-
drivers/cxl/core/mbox.c | 96 ++--
drivers/cxl/core/memdev.c | 41 +-
drivers/cxl/core/pci.c | 168 +++----
drivers/cxl/core/port.c | 208 +++++----
drivers/cxl/core/region.c | 81 ++--
drivers/cxl/cxl.h | 9 +-
drivers/cxl/cxlmem.h | 27 +-
drivers/cxl/mem.c | 29 +-
drivers/cxl/pci.c | 91 ++--
drivers/cxl/pmem.c | 26 +-
drivers/cxl/port.c | 2 +-
drivers/cxl/security.c | 23 +-
include/{linux/einj-cxl.h => cxl/einj.h} | 0
include/{linux/cxl-event.h => cxl/event.h} | 0
include/cxl/mailbox.h | 28 ++
tools/testing/cxl/Kbuild | 2 +-
tools/testing/cxl/mock_acpi.c | 2 +-
tools/testing/cxl/test/mem.c | 44 +-
tools/testing/cxl/test/mock.c | 10 +-
26 files changed, 1092 insertions(+), 406 deletions(-)
create mode 100644 Documentation/driver-api/cxl/access-coordinates.rst
rename include/{linux/einj-cxl.h => cxl/einj.h} (100%)
rename include/{linux/cxl-event.h => cxl/event.h} (100%)
create mode 100644 include/cxl/mailbox.h
next reply other threads:[~2024-09-27 14:03 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-27 14:02 Dave Jiang [this message]
2024-09-27 16:22 ` [GIT PULL] Compute Express Link (CXL) for 6.12 Linus Torvalds
2024-09-27 16:55 ` Dave Jiang
2024-09-27 20:00 ` pr-tracker-bot
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