messages from 2023-06-01 10:17:54 to 2023-06-08 11:02:01 UTC [more...]
[PATCH v2 0/4] cxl: Add a firmware update mechanism and cxl_test emulation
2023-06-08 11:01 UTC (8+ messages)
` [PATCH v2 1/4] cxl: add a firmware update mechanism using the sysfs firmware loader
` [PATCH v2 2/4] tools/testing/cxl: Fix command effects for inject/clear poison
` [PATCH v2 3/4] tools/testing/cxl: Use named effects for the Command Effect Log
` [PATCH v2 4/4] tools/testing/cxl: add firmware update emulation to CXL memdevs
[PATCH 00/19] cxl: Device memory setup
2023-06-08 10:47 UTC (42+ messages)
` [PATCH 01/19] cxl/regs: Clarify when a 'struct cxl_register_map' is input vs output
` [PATCH 02/19] tools/testing/cxl: Remove unused @cxlds argument
` [PATCH 03/19] cxl/mbox: Move mailbox related driver state to its own data structure
` [PATCH 04/19] cxl/memdev: Make mailbox functionality optional
` [PATCH 05/19] cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTMEM, DEVMEM}
` [PATCH 06/19] cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM
` [PATCH 07/19] cxl/region: Manage decoder target_type at decoder-attach time
` [PATCH 08/19] cxl/port: Enumerate flit mode capability
` [PATCH 09/19] cxl/memdev: Formalize endpoint port linkage
` [PATCH 10/19] cxl/memdev: Indicate probe deferral
` [PATCH 11/19] cxl/region: Factor out construct_region_{begin, end} and drop_region() for reuse
` [PATCH 12/19] cxl/region: Factor out interleave ways setup
` [PATCH 13/19] cxl/region: Factor out interleave granularity setup
` [PATCH 14/19] cxl/region: Clarify locking requirements of cxl_region_attach()
` [PATCH 15/19] cxl/region: Specify host-only vs device memory at region creation time
` [PATCH 16/19] cxl/hdm: Define a driver interface for DPA allocation
` [PATCH 17/19] cxl/region: Define a driver interface for HPA free space enumeration
` [PATCH 18/19] cxl/region: Define a driver interface for region creation
` [PATCH 19/19] tools/testing/cxl: Emulate a CXL accelerator with local memory
[PATCH v5 00/26] cxl/pci: Add support for RCH RAS error handling
2023-06-08 10:36 UTC (35+ messages)
` [PATCH v5 01/26] cxl/acpi: Probe RCRB later during RCH downstream port creation
` [PATCH v5 02/26] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
` [PATCH v5 03/26] cxl: Rename member @dport of struct cxl_dport to @dev
` [PATCH v5 04/26] cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
` [PATCH v5 05/26] cxl/core/regs: Add @dev to cxl_register_map
` [PATCH v5 06/26] cxl/pci: Refactor component register discovery for reuse
` [PATCH v5 07/26] cxl/acpi: Moving add_host_bridge_uport() around
` [PATCH v5 08/26] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port
` [PATCH v5 09/26] cxl/regs: Remove early capability checks in Component Register setup
` [PATCH v5 10/26] cxl/mem: Prepare for early RCH dport component register setup
` [PATCH v5 11/26] cxl/pci: Early setup RCH dport component registers from RCRB
` [PATCH v5 12/26] cxl/port: Store the port's Component Register mappings in struct cxl_port
` [PATCH v5 13/26] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport
` [PATCH v5 14/26] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
` Concept of LD-ID in QEMU
` [PATCH v5 15/26] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
` [PATCH v5 16/26] cxl/port: Remove Component Register base address from struct cxl_port
` [PATCH v5 17/26] cxl/port: Remove Component Register base address from struct cxl_dport
` [PATCH v5 18/26] cxl/pci: Remove Component Register base address from struct cxl_dev_state
` [PATCH v5 19/26] cxl/pci: Add RCH downstream port AER register discovery
` [PATCH v5 20/26] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
` [PATCH v5 21/26] cxl/pci: Update CXL error logging to use RAS register address
` [PATCH v5 22/26] cxl/pci: Map RCH downstream AER registers for logging protocol errors
` [PATCH v5 23/26] cxl/pci: Disable root port interrupts in RCH mode
` [PATCH v5 24/26] cxl/pci: Add RCH downstream port error logging
` [PATCH v5 25/26] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler
` [PATCH v5 26/26] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
[Qemu RFC 0/7] Early enabling of DCD emulation in Qemu
2023-06-08 9:43 UTC (7+ messages)
Questions about CXL device (type 3 memory) hotplug
2023-06-08 7:39 UTC (21+ messages)
[PATCH 0/2] CXL: Apply SRAT defined PXM to entire CFMWS window
2023-06-07 10:44 UTC (6+ messages)
` [PATCH 1/2] x86/numa: Introduce numa_fill_memblks()
[PATCH 0/4] dax: Fix use after free and other cleanups
2023-06-06 20:42 UTC (13+ messages)
` [PATCH 1/4] dax: Fix dax_mapping_release() use after free
` [PATCH 2/4] dax: Use device_unregister() in unregister_dax_mapping()
` [PATCH 3/4] dax: Introduce alloc_dev_dax_id()
` [PATCH 4/4] dax: Cleanup extra dax_region references
[PATCH v4 00/23] cxl/pci: Add support for RCH RAS error handling
2023-06-02 15:58 UTC (52+ messages)
` [PATCH v4 01/23] cxl/acpi: Probe RCRB later during RCH downstream port creation
` [PATCH v4 02/23] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
` [PATCH v4 03/23] cxl: Rename member @dport of struct cxl_dport to @dev
` [PATCH v4 04/23] cxl/core/regs: Add @dev to cxl_register_map
` [PATCH v4 05/23] cxl/pci: Refactor component register discovery for reuse
` [PATCH v4 06/23] cxl/acpi: Moving add_host_bridge_uport() around
` [PATCH v4 07/23] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port
` [PATCH v4 08/23] cxl/regs: Remove early capability checks in Component Register setup
` [PATCH v4 09/23] cxl/pci: Early setup RCH dport component registers from RCRB
` [PATCH v4 10/23] cxl/port: Store the port's Component Register mappings in struct cxl_port
` [PATCH v4 11/23] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport
` [PATCH v4 12/23] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
` [PATCH v4 13/23] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
` [PATCH v4 14/23] cxl/port: Remove Component Register base address from struct cxl_port
` [PATCH v4 15/23] cxl/port: Remove Component Register base address from struct cxl_dport
` [PATCH v4 16/23] cxl/pci: Remove Component Register base address from struct cxl_dev_state
` [PATCH v4 17/23] cxl/pci: Add RCH downstream port AER register discovery
` [PATCH v4 19/23] cxl/pci: Update CXL error logging to use RAS register address
` [PATCH v4 20/23] cxl/pci: Prepare for logging RCH downstream port protocol errors
` [PATCH v4 21/23] cxl/pci: Add RCH downstream port error logging
` [PATCH v4 22/23] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler
[PATCH v3 0/4] acpi: Add CDAT parsing support to ACPI tables code
2023-06-06 1:36 UTC (11+ messages)
` [PATCH v3 1/4] acpi: Move common tables helper functions to common lib
` [PATCH v3 2/4] lib/firmware_table: tables: Add CDAT table parsing support
` [PATCH v3 3/4] acpi: fix misnamed define for CDAT DSMAS
` [PATCH v3 4/4] acpi: Add defines for CDAT SSLBIS
[PATCH ndctl v2 0/5] cxl: firmware update support for libcxl and cxl-cli
2023-06-05 20:21 UTC (6+ messages)
` [PATCH ndctl v2 1/5] cxl/memdev.c: allow filtering memdevs by bus
` [PATCH ndctl v2 2/5] cxl/list: print firmware info in memdev listings
` [PATCH ndctl v2 3/5] cxl/fw_loader: add APIs to get current state of the FW loader mechanism
` [PATCH ndctl v2 4/5] cxl: add an update-firmware command
` [PATCH ndctl v2 5/5] test/cxl-update-firmware: add a unit test for firmware update
[PATCH] dax/hmem: Fix refcount leak in dax_hmem_probe()
2023-06-03 4:11 UTC (4+ messages)
[PATCH RFC 0/4] dax: Clean up dax_region references
2023-06-03 2:09 UTC (5+ messages)
` [PATCH RFC 1/4] dax/bus: Fix leaked reference in alloc_dax_region()
` [PATCH RFC 2/4] dax/hmem: Fix refcount leak in dax_hmem_probe()
` [PATCH RFC 3/4] dax/cxl: Fix refcount leak in cxl_dax_region_probe()
` [PATCH RFC 4/4] dax/bus: Remove unnecessary reference in alloc_dax_region()
I2C Multi-master and Controller Slave Mode in QEMU
2023-06-02 23:58 UTC (9+ messages)
` [EXT] "
[RFC PATCH 0/5] CXL FM initial infrastructure
2023-06-02 21:37 UTC (6+ messages)
` [RFC PATCH 1/5] CXL FM: create initial project infrastructure
` [RFC PATCH 2/5] CXL FM: [lib] introduce CXL FM library
` [RFC PATCH 3/5] CXL FM: [fm_daemon] introduce CXL FM daemon
` [RFC PATCH 4/5] CXL FM: [fm_orchestrator] introduce CXL FM orchestrator
` [RFC PATCH 5/5] CXL FM: [fm_cli] introduce CXL FM CLI tool
[PATCH 0/4] cxl: Add a firmware update mechanism and cxl_test emulation
2023-06-02 18:01 UTC (6+ messages)
` [PATCH 4/4] tools/testing/cxl: add firmware update emulation to CXL memdevs
[PATCH v4 23/23] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
2023-06-02 16:41 UTC (4+ messages)
[RFC] cxl: Multi-headed device design
2023-06-02 13:02 UTC (6+ messages)
[PATCH] cxl/port: Enable the HDM decoder capability for switch ports
2023-06-02 8:34 UTC (4+ messages)
[ndctl PATCH] cxl/region: Fix memdevs leak
2023-06-01 17:53 UTC (2+ messages)
[PATCH v5 0/6] cxl: Support device sanitation
2023-06-01 17:24 UTC (3+ messages)
` [PATCH 5/6] cxl/mem: Support Secure Erase
[PATCH v6 00/11] cxl: Add support for QTG ID retrieval for CXL subsystem
2023-06-01 17:13 UTC (8+ messages)
` [PATCH v6 06/11] cxl: Store the access coordinates for the generic ports
` [PATCH v6 09/11] cxl: Store QTG IDs and related info to the CXL memory device context
` [PATCH v6 10/11] cxl: Export sysfs attributes for memory device QoS class
[PATCH v2 0/4] acpi: numa: Add target support for generic port to HMAT parsing
2023-06-01 16:48 UTC (5+ messages)
` [PATCH v2 3/4] acpi: numa: Add setting of generic port system locality attributes
[PATCH v2 0/4] acpi: Add CDAT parsing support to ACPI tables code
2023-06-01 15:38 UTC (4+ messages)
` [PATCH v2 1/4] acpi: Move common tables helper functions to common lib
[PATCH v2] ACPI, APEI, EINJ: Remove memory range validation for CXL error types
2023-06-01 14:45 UTC (5+ messages)
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