messages from 2023-06-04 23:31:46 to 2023-06-13 21:23:46 UTC [more...]
[PATCH 00/19] cxl: Device memory setup
2023-06-13 21:23 UTC (47+ messages)
` [PATCH 01/19] cxl/regs: Clarify when a 'struct cxl_register_map' is input vs output
` [PATCH 02/19] tools/testing/cxl: Remove unused @cxlds argument
` [PATCH 03/19] cxl/mbox: Move mailbox related driver state to its own data structure
` [PATCH 04/19] cxl/memdev: Make mailbox functionality optional
` [PATCH 05/19] cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTMEM, DEVMEM}
` [PATCH 06/19] cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM
` [PATCH 07/19] cxl/region: Manage decoder target_type at decoder-attach time
` [PATCH 08/19] cxl/port: Enumerate flit mode capability
` [PATCH 09/19] cxl/memdev: Formalize endpoint port linkage
` [PATCH 10/19] cxl/memdev: Indicate probe deferral
` [PATCH 11/19] cxl/region: Factor out construct_region_{begin, end} and drop_region() for reuse
` [PATCH 12/19] cxl/region: Factor out interleave ways setup
` [PATCH 13/19] cxl/region: Factor out interleave granularity setup
` [PATCH 14/19] cxl/region: Clarify locking requirements of cxl_region_attach()
` [PATCH 15/19] cxl/region: Specify host-only vs device memory at region creation time
` [PATCH 16/19] cxl/hdm: Define a driver interface for DPA allocation
` [PATCH 17/19] cxl/region: Define a driver interface for HPA free space enumeration
` [PATCH 18/19] cxl/region: Define a driver interface for region creation
` [PATCH 19/19] tools/testing/cxl: Emulate a CXL accelerator with local memory
[PATCH v3 0/4] cxl: Add a firmware update mechanism and cxl_test emulation
2023-06-13 18:41 UTC (9+ messages)
` [PATCH v3 1/4] cxl: add a firmware update mechanism using the sysfs firmware loader
` [PATCH v3 2/4] tools/testing/cxl: Fix command effects for inject/clear poison
` [PATCH v3 3/4] tools/testing/cxl: Use named effects for the Command Effect Log
` [PATCH v3 4/4] tools/testing/cxl: add firmware update emulation to CXL memdevs
[PATCH v6 0/7] cxl: Support device sanitation
2023-06-13 18:12 UTC (15+ messages)
` [PATCH 1/7] cxl/mbox: Allow for IRQ_NONE case in the isr
` [PATCH 2/7] cxl/mem: Introduce security state sysfs file
` [PATCH 3/7] cxl/mbox: Add sanitation handling machinery
` [PATCH 4/7] cxl/mem: Wire up Sanitation support
` [PATCH 5/7] cxl/test: Add Sanitize opcode support
` [PATCH 6/7] cxl/mem: Support Secure Erase
` [PATCH 7/7] cxl/test: Add Secure Erase opcode support
[PATCH v2] base/node / acpi: Change 'node_hmem_attrs' to 'access_coordinates'
2023-06-13 16:19 UTC (3+ messages)
[PATCH v5 00/26] cxl/pci: Add support for RCH RAS error handling
2023-06-13 15:28 UTC (72+ messages)
` [PATCH v5 01/26] cxl/acpi: Probe RCRB later during RCH downstream port creation
` [PATCH v5 02/26] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
` [PATCH v5 03/26] cxl: Rename member @dport of struct cxl_dport to @dev
` [PATCH v5 04/26] cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
` [PATCH v5 05/26] cxl/core/regs: Add @dev to cxl_register_map
` [PATCH v5 06/26] cxl/pci: Refactor component register discovery for reuse
` [PATCH v5 07/26] cxl/acpi: Moving add_host_bridge_uport() around
` [PATCH v5 08/26] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port
` [PATCH v5 09/26] cxl/regs: Remove early capability checks in Component Register setup
` [PATCH v5 10/26] cxl/mem: Prepare for early RCH dport component register setup
` [PATCH v5 11/26] cxl/pci: Early setup RCH dport component registers from RCRB
` [PATCH v5 12/26] cxl/port: Store the port's Component Register mappings in struct cxl_port
` [PATCH v5 13/26] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport
` [PATCH v5 14/26] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
` Concept of LD-ID in QEMU
` [EXT] "
` [PATCH v5 15/26] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
` [PATCH v5 16/26] cxl/port: Remove Component Register base address from struct cxl_port
` [PATCH v5 17/26] cxl/port: Remove Component Register base address from struct cxl_dport
` [PATCH v5 18/26] cxl/pci: Remove Component Register base address from struct cxl_dev_state
` [PATCH v5 19/26] cxl/pci: Add RCH downstream port AER register discovery
` [PATCH v5 20/26] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
` [PATCH v5 21/26] cxl/pci: Update CXL error logging to use RAS register address
` [PATCH v5 22/26] cxl/pci: Map RCH downstream AER registers for logging protocol errors
` [PATCH v5 23/26] cxl/pci: Disable root port interrupts in RCH mode
` [PATCH v5 24/26] cxl/pci: Add RCH downstream port error logging
` [PATCH v5 25/26] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler
` [PATCH v5 26/26] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
[PATCH v3 0/4] acpi: Add CDAT parsing support to ACPI tables code
2023-06-12 20:47 UTC (8+ messages)
` [PATCH v3 1/4] acpi: Move common tables helper functions to common lib
[Qemu RFC 0/7] Early enabling of DCD emulation in Qemu
2023-06-10 0:28 UTC (13+ messages)
` [EXT] "
[PATCH v2 0/4] cxl: Add a firmware update mechanism and cxl_test emulation
2023-06-09 11:08 UTC (15+ messages)
` [PATCH v2 1/4] cxl: add a firmware update mechanism using the sysfs firmware loader
` [PATCH v2 2/4] tools/testing/cxl: Fix command effects for inject/clear poison
` [PATCH v2 3/4] tools/testing/cxl: Use named effects for the Command Effect Log
` [PATCH v2 4/4] tools/testing/cxl: add firmware update emulation to CXL memdevs
Questions about CXL device (type 3 memory) hotplug
2023-06-09 1:02 UTC (25+ messages)
[PATCH 0/2] CXL: Apply SRAT defined PXM to entire CFMWS window
2023-06-07 10:44 UTC (6+ messages)
` [PATCH 1/2] x86/numa: Introduce numa_fill_memblks()
[PATCH 0/4] dax: Fix use after free and other cleanups
2023-06-06 20:42 UTC (8+ messages)
` [PATCH 4/4] dax: Cleanup extra dax_region references
` [PATCH 1/4] dax: Fix dax_mapping_release() use after free
` [PATCH 2/4] dax: Use device_unregister() in unregister_dax_mapping()
[PATCH v4 00/23] cxl/pci: Add support for RCH RAS error handling
2023-06-01 13:36 UTC (3+ messages)
` [PATCH v4 17/23] cxl/pci: Add RCH downstream port AER register discovery
[PATCH ndctl v2 0/5] cxl: firmware update support for libcxl and cxl-cli
2023-06-05 20:21 UTC (6+ messages)
` [PATCH ndctl v2 1/5] cxl/memdev.c: allow filtering memdevs by bus
` [PATCH ndctl v2 2/5] cxl/list: print firmware info in memdev listings
` [PATCH ndctl v2 3/5] cxl/fw_loader: add APIs to get current state of the FW loader mechanism
` [PATCH ndctl v2 4/5] cxl: add an update-firmware command
` [PATCH ndctl v2 5/5] test/cxl-update-firmware: add a unit test for firmware update
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