messages from 2023-06-21 00:07:01 to 2023-06-30 23:19:44 UTC [more...]
[PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling
2023-06-30 23:16 UTC (10+ messages)
` [PATCH v8 01/14] cxl/port: Pre-initialize component register mappings
` [PATCH v8 02/14] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
` [PATCH v8 03/14] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
` [PATCH v8 04/14] cxl/pci: Remove Component Register base address from struct cxl_dev_state
` [PATCH v8 05/14] cxl/port: Remove Component Register base address from struct cxl_port
` [PATCH v8 06/14] cxl/pci: Add RCH downstream port AER register discovery
` [PATCH v8 07/14] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
` [PATCH v8 08/14] cxl/pci: Update CXL error logging to use RAS register address
` [PATCH v8 09/14] cxl/pci: Map RCH downstream AER registers for logging protocol errors
[PATCH v7 00/27] cxl/pci: Add support for RCH RAS error handling
2023-06-30 19:56 UTC (43+ messages)
` [PATCH v7 01/27] cxl/acpi: Probe RCRB later during RCH downstream port creation
` [PATCH v7 02/27] cxl: Updates for CXL Test to work with RCH
` [PATCH v7 03/27] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
` [PATCH v7 04/27] cxl: Rename member @dport of struct cxl_dport to @dport_dev
` [PATCH v7 05/27] cxl: Rename 'uport' to 'uport_dev'
` [PATCH v7 06/27] cxl/core/regs: Add @dev to cxl_register_map
` [PATCH v7 07/27] cxl/pci: Refactor component register discovery for reuse
` [PATCH v7 08/27] cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs()
` [PATCH v7 09/27] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port
` [PATCH v7 10/27] cxl/port: Remove Component Register base address from struct cxl_dport
` [PATCH v7 11/27] cxl/regs: Remove early capability checks in Component Register setup
` [PATCH v7 12/27] cxl/mem: Prepare for early RCH dport component register setup
` [PATCH v7 13/27] cxl/pci: Early setup RCH dport component registers from RCRB
` [PATCH v7 14/27] cxl/port: Store the port's Component Register mappings in struct cxl_port
` [PATCH v7 15/27] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport
` [PATCH v7 16/27] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
` [PATCH v7 17/27] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
` [PATCH v7 18/27] cxl/port: Remove Component Register base address from struct cxl_port
` [PATCH v7 19/27] cxl/pci: Add RCH downstream port AER register discovery
` [PATCH v7 20/27] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
` [PATCH v7 21/27] cxl/pci: Update CXL error logging to use RAS register address
` [PATCH v7 22/27] cxl/pci: Map RCH downstream AER registers for logging protocol errors
` [PATCH v7 23/27] cxl/pci: Add RCH downstream port error logging
` [PATCH v7 24/27] cxl/pci: Disable root port interrupts in RCH mode
` [PATCH v7 25/27] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler
` [PATCH v7 26/27] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
` [PATCH v7 27/27] cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
[Qemu RFC 0/7] Early enabling of DCD emulation in Qemu
2023-06-30 19:34 UTC (13+ messages)
` [RFC 2/7] hw/cxl/cxl-mailbox-utils: Add dynamic capacity region representative and mailbox command support
` [RFC 7/7] hw/mem/cxl_type3: add read/write support to dynamic capacity
` [RFC 5/7] hw/cxl/cxl-mailbox-utils: Add mailbox commands to support add/release dynamic capacity response
[NDCTL PATCH] cxl/region: Always use the correct target position
2023-06-30 15:12 UTC
[PATCH v3] dax/kmem: Pass valid argument to memory_group_register_static
2023-06-30 3:41 UTC (2+ messages)
[PATCH -next] cxl: Fix one kernel-doc comment
2023-06-29 23:22 UTC (2+ messages)
[Question] How to set up DVSEC CXL Range Registers for DCD devices
2023-06-29 17:10 UTC
[PATCH 0/5] cxl/dcd: Add support for Dynamic Capacity Devices (DCD)
2023-06-29 15:30 UTC (24+ messages)
` [PATCH 1/5] cxl/mem : Read Dynamic capacity configuration from the device
` [PATCH 2/5] cxl/region: Add dynamic capacity cxl region support
` [PATCH 4/5] cxl/mem: Add support to handle DCD add and release capacity events
[cxl:next] BUILD SUCCESS 71baec7b8500c92f9723f39d06a7ae465483da1f
2023-06-28 13:38 UTC
[PATCH v6 0/7] cxl: Support device sanitation
2023-06-27 23:01 UTC (12+ messages)
` [PATCH 3/7] cxl/mbox: Add sanitation handling machinery
` [PATCH 4/7] cxl/mem: Wire up Sanitation support
` [PATCH] cxl/pci: Use correct flag for sanitize polling
[ndctl PATCH v3 0/6] cxl/monitor and ndctl/monitor fixes
2023-06-27 10:17 UTC (2+ messages)
[cxl:pending] BUILD SUCCESS 0c0df63177e37ae826d803280eb2c5b6b6a7a9a4
2023-06-27 1:20 UTC
[PATCH v3 0/2] CXL: Apply SRAT defined PXM to entire CFMWS window
2023-06-27 0:49 UTC (5+ messages)
` [PATCH v3 1/2] x86/numa: Introduce numa_fill_memblks()
` [PATCH v3 2/2] ACPI: NUMA: Apply SRAT proximity domain to entire CFMWS window
[PATCH v8 0/5] perf: CXL 3.0 Performance Monitoring Unit support
2023-06-26 0:46 UTC (3+ messages)
` [PATCH v8 3/5] cxl/pci: Find and register CXL PMU devices
[PATCH 0/3] cxl/region: Cache management and region decode reset fixes
2023-06-25 20:42 UTC (9+ messages)
` [PATCH 1/3] cxl/region: Move cache invalidation before region teardown, and before setup
` [PATCH 2/3] cxl/region: Flag partially torn down regions as unusable
` [PATCH 3/3] cxl/region: Fix state transitions after reset failure
[PATCH 0/2] cxl/region: Improve Soft Reserved resource handling
2023-06-24 1:24 UTC (3+ messages)
` [PATCH 1/2] cxl/region: Try to add a region resource to a soft reserved parent
` [PATCH 2/2] cxl/region: Remove a soft reserved resource at region teardown
How to find the base address of CXL 1.1 Downstream Port RCRB for specific device
2023-06-23 21:46 UTC
[PATCH v6 00/27] cxl/pci: Add support for RCH RAS error handling
2023-06-23 13:28 UTC (63+ messages)
` [PATCH v6 01/27] cxl/port: Fix NULL pointer access in devm_cxl_add_port()
` [PATCH v6 02/27] cxl/acpi: Probe RCRB later during RCH downstream port creation
` [PATCH v6 03/27] cxl: Updates for CXL Test to work with RCH
` [PATCH v6 04/27] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
` [PATCH v6 05/27] cxl: Rename member @dport of struct cxl_dport to @dport_dev
` [PATCH v6 06/27] cxl: Rename 'uport' to 'uport_dev'
` [PATCH v6 07/27] cxl/core/regs: Add @dev to cxl_register_map
` [PATCH v6 08/27] cxl/pci: Refactor component register discovery for reuse
` [PATCH v6 09/27] cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs()
` [PATCH v6 10/27] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port
` [PATCH v6 11/27] cxl/port: Remove Component Register base address from struct cxl_dport
` [PATCH v6 12/27] cxl/regs: Remove early capability checks in Component Register setup
` [PATCH v6 13/27] cxl/mem: Prepare for early RCH dport component register setup
` [PATCH v6 14/27] cxl/pci: Early setup RCH dport component registers from RCRB
` [PATCH v6 15/27] cxl/port: Store the port's Component Register mappings in struct cxl_port
` [PATCH v6 16/27] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport
` [PATCH v6 17/27] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
` [PATCH v6 18/27] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
` [PATCH v6 19/27] cxl/port: Remove Component Register base address from struct cxl_port
` [PATCH v6 20/27] cxl/pci: Add RCH downstream port AER register discovery
` [PATCH v6 21/27] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
` [PATCH v6 22/27] cxl/pci: Update CXL error logging to use RAS register address
` [PATCH v6 23/27] cxl/pci: Map RCH downstream AER registers for logging protocol errors
` [PATCH v6 24/27] cxl/pci: Add RCH downstream port error logging
` [PATCH v6 25/27] cxl/pci: Disable root port interrupts in RCH mode
` [PATCH v6 26/27] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler
` [PATCH v6 27/27] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
[PATCH 0/3] mm: use memmap_on_memory semantics for dax/kmem
2023-06-23 12:35 UTC (9+ messages)
` [PATCH 1/3] mm/memory_hotplug: Allow an override for the memmap_on_memory param
[PATCH v8 0/4] hw/cxl: Poison get, inject, clear
2023-06-23 12:13 UTC (4+ messages)
[PATCH v4 0/6] acpi: numa: add target support for generic port to HMAT parsing
2023-06-22 21:40 UTC (7+ messages)
` [PATCH v4 1/6] acpi: numa: Create enum for memory_target access coordinates indexing
` [PATCH v4 2/6] ACPICA: Add a define for size of acpi_srat_generic_affinity DeviceHandle
` [PATCH v4 3/6] acpi: numa: Add genport target allocation to the HMAT parsing
` [PATCH v4 4/6] acpi: Break out nesting for hmat_parse_locality()
` [PATCH v4 5/6] acpi: numa: Add setting of generic port system locality attributes
` [PATCH v4 6/6] acpi: numa: Add helper function to retrieve the performance attributes
[PATCH v3 0/6] acpi: numa: add target support for generic port to HMAT parsing
2023-06-22 18:41 UTC (8+ messages)
` [PATCH v3 3/6] acpi: numa: Add genport target allocation to the "
` [PATCH v3 4/6] acpi: Break out nesting for hmat_parse_locality()
` [PATCH v3 5/6] acpi: numa: Add setting of generic port system locality attributes
[BUG] Root port fails to match with port driver on non-RCH topology
2023-06-22 14:47 UTC (6+ messages)
[PATCH v2 00/12] Device memory prep
2023-06-22 14:04 UTC (16+ messages)
` [PATCH v2 03/12] cxl: Fix kernel-doc warnings
` [PATCH v2 04/12] cxl: Remove leftover attribute documentation in 'struct cxl_dev_state'
` [PATCH v2 06/12] cxl/memdev: Make mailbox functionality optional
` [PATCH v2 10/12] cxl/pci: Unconditionally unmask 256B Flit errors
` [PATCH v2 11/12] cxl/port: Enumerate cxl link capabilities
[PATCH v7 00/11] cxl: Add support for QTG ID retrieval for CXL subsystem
2023-06-22 13:28 UTC (3+ messages)
` [PATCH v7 10/11] cxl: Export sysfs attributes for memory device QoS class
[PATCH] Revert "cxl/port: Enable the HDM decoder capability for switch ports"
2023-06-22 9:22 UTC (3+ messages)
[PATCH] dax/kmem: Pass valid argument to memory_group_register_static
2023-06-22 7:15 UTC (5+ messages)
[PATCH v2] dax/kmem: Pass valid argument to memory_group_register_static
2023-06-21 10:34 UTC
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