messages from 2023-08-25 11:55:19 to 2023-09-05 19:56:46 UTC [more...]
[PATCH RFC v2 00/18] DCD: Add support for Dynamic Capacity Devices (DCD)
2023-09-05 17:55 UTC (61+ messages)
` [PATCH RFC v2 01/18] cxl/hdm: Debug, use decoder name function
` [PATCH RFC v2 02/18] cxl/mbox: Flag support for Dynamic Capacity Devices (DCD)
` [PATCH RFC v2 03/18] cxl/mem: Read Dynamic capacity configuration from the device
` [PATCH RFC v2 04/18] cxl/region: Add Dynamic Capacity decoder and region modes
` [PATCH RFC v2 05/18] cxl/port: Add Dynamic Capacity mode support to endpoint decoders
` [PATCH RFC v2 06/18] cxl/port: Add Dynamic Capacity size "
` [PATCH RFC v2 07/18] cxl/mem: Expose device dynamic capacity configuration
` [PATCH RFC v2 08/18] cxl/region: Add Dynamic Capacity CXL region support
` [PATCH RFC v2 09/18] cxl/mem: Read extents on memory device discovery
` [PATCH RFC v2 10/18] cxl/mem: Handle DCD add and release capacity events
` [PATCH RFC v2 11/18] cxl/region: Expose DC extents on region driver load
` [PATCH RFC v2 12/18] cxl/region: Notify regions of DC changes
` [PATCH RFC v2 13/18] dax/bus: Factor out dev dax resize logic
` [PATCH RFC v2 14/18] dax/region: Support DAX device creation on dynamic DAX regions
` [PATCH RFC v2 15/18] cxl/mem: Trace Dynamic capacity Event Record
` [PATCH RFC v2 16/18] tools/testing/cxl: Make event logs dynamic
` [PATCH RFC v2 17/18] tools/testing/cxl: Add DC Regions to mock mem data
` [PATCH RFC v2 18/18] tools/testing/cxl: Add Dynamic Capacity events
[PATCH v3 0/2] cxl/region: Improve Soft Reserved resource handling
2023-09-05 17:42 UTC (6+ messages)
` [PATCH v3 2/2] cxl/region: Remove a soft reserved resource at region teardown
[PATCH v3 0/3] CXL, ACPI, APEI, EINJ: Update EINJ for CXL 1.1 error types
2023-09-05 18:44 UTC (4+ messages)
` [PATCH v3 1/3] CXL, PCIE: Add cxl_rcrb_addr file to dport_dev
` [PATCH v3 2/3] ACPI, APEI, EINJ: Add CXL 1.1 EINJ error type support
` [PATCH v3 3/3] ACPI, APEI, EINJ: Update EINJ documentation
[PATCH 0/2] hw/cxl: Support emulating 4 HDM decoders throughout topology
2023-09-05 16:55 UTC (9+ messages)
` [PATCH 1/2] hw/cxl: Add utility functions decoder interleave ways and target count
` [PATCH 2/2] hw/cxl: Support 4 HDM decoders at all levels of topology
[PATCH v2] cxl/region: Refactor granularity select in cxl_port_setup_targets()
2023-09-05 17:29 UTC (4+ messages)
[PATCH v10 00/15] cxl/pci: Add support for RCH RAS error handling
2023-09-05 16:55 UTC (13+ messages)
` [PATCH v10 01/15] cxl/port: Pre-initialize component register mappings
` [PATCH v10 02/15] cxl/regs: Prepare for multiple users of "
` [PATCH v10 03/15] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
` [PATCH v10 04/15] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
` [PATCH v10 05/15] cxl/pci: Remove Component Register base address from struct cxl_dev_state
` [PATCH v10 06/15] cxl/port: Remove Component Register base address from struct cxl_port
` [PATCH v10 07/15] cxl/pci: Add RCH downstream port AER register discovery
[PATCH] hw/pci-bridge/cxl-upstream: Add serial number extended capability support
2023-09-05 16:21 UTC (4+ messages)
[PATCH] perf: CXL: fix mismatched number of counters mask
2023-09-05 16:01 UTC (5+ messages)
[ndctl PATCH v2 0/2] Add support for Set Alert Configuration mailbox command
2023-09-05 6:29 UTC (4+ messages)
` [ndctl PATCH v2 2/2] cxl: add 'set-alert-config' command to cxl tool
[PATCH 0/5 v2] CXL: SK hynix Niagara MHSLD Device
2023-09-05 9:04 UTC (15+ messages)
` [PATCH 1/5] cxl/mailbox: move mailbox effect definitions to a header
` [PATCH 2/5] cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions
` [PATCH 3/5] cxl/type3: Expose ct3 functions so that inheriters can call them
` [PATCH 4/5] cxl/type3: add an optional mhd validation function for memory accesses
` [PATCH 5/5] cxl/vendor: SK hynix Niagara Multi-Headed SLD Device
[PATCH] cxl/mbox: Fix CEL logic for poison and security commands
2023-09-04 17:24 UTC (3+ messages)
[PATCH v2 0/3] hw/cxl: Add dummy ACPI QTG DSM
2023-09-04 16:18 UTC (4+ messages)
` [PATCH v2 1/3] tests/acpi: Allow update of DSDT.cxl
` [PATCH v2 2/3] hw/cxl: Add QTG _DSM support for ACPI0017 device
` [PATCH v2 3/3] tests/acpi: Update DSDT.cxl with QTG DSM
[PATCH 0/4] hw/cxl: Minor CXL emulation fixes and cleanup
2023-09-04 13:46 UTC (8+ messages)
` [PATCH 1/4] hw/cxl: Fix CFMW config memory leak
` [PATCH 2/4] hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBIS
` [PATCH 3/4] hw/cxl/cxl_device: Replace magic number in CXLError definition
` [PATCH 4/4] docs/cxl: Change to lowercase as others
[PATCH] cxl/hdm: Debug, use decoder name function
2023-09-03 2:52 UTC
Support for CXL v3.0 spec with QEMU
2023-09-02 14:58 UTC (12+ messages)
[PATCH v9 00/15] cxl/pci: Add support for RCH RAS error handling
2023-09-01 9:10 UTC (25+ messages)
` [PATCH v9 01/15] cxl/port: Pre-initialize component register mappings
` [PATCH v9 02/15] cxl/regs: Prepare for multiple users of "
` [PATCH v9 03/15] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
` [PATCH v9 04/15] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
` [PATCH v9 05/15] cxl/pci: Remove Component Register base address from struct cxl_dev_state
` [PATCH v9 06/15] cxl/port: Remove Component Register base address from struct cxl_port
` [PATCH v9 07/15] cxl/pci: Add RCH downstream port AER register discovery
` [PATCH v9 08/15] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
` [PATCH v9 09/15] cxl/pci: Update CXL error logging to use RAS register address
` [PATCH v9 10/15] cxl/pci: Map RCH downstream AER registers for logging protocol errors
` [PATCH v9 11/15] cxl/pci: Add RCH downstream port error logging
` [PATCH v9 12/15] cxl/pci: Disable root port interrupts in RCH mode
` [PATCH v9 13/15] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler
` [PATCH v9 14/15] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
` [PATCH v9 15/15] cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
[PATCH 0/4] CXL: SK hynix Niagara MHSLD Device
2023-09-01 9:05 UTC (5+ messages)
` [PATCH 3/4] cxl/type3: minimum MHD cci support
[PATCH v10 08/15] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
2023-08-31 20:35 UTC (9+ messages)
` [PATCH v10 09/15] cxl/pci: Update CXL error logging to use RAS register address
` [PATCH v10 10/15] cxl/pci: Map RCH downstream AER registers for logging protocol errors
` [PATCH v10 11/15] cxl/pci: Add RCH downstream port error logging
` [PATCH v10 12/15] cxl/pci: Disable root port interrupts in RCH mode
` [PATCH v10 13/15] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler
` [PATCH v10 14/15] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
` [PATCH v10 15/15] cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
[Qemu PATCH v2 0/9] Enabling DCD emulation support in Qemu
2023-08-30 15:37 UTC (9+ messages)
` [Qemu PATCH v2 9/9] hw/mem/cxl_type3: Add dpa range validation for accesses to dc regions
[PATCH] cxl: Add Support for Get Timestamp
2023-08-30 17:37 UTC (3+ messages)
[PATCH] cxl/region: Clarify pointers in unregister_region()
2023-08-30 17:36 UTC (4+ messages)
[PATCH v2] cxl/region: Match auto-discovered region decoders by HPA range
2023-08-29 13:21 UTC (2+ messages)
[PATCH v3] fs: clean up usage of noop_dirty_folio
2023-08-29 8:11 UTC (2+ messages)
QEMU freeze with CXL memory in Normal zone and stress-ng
2023-08-28 23:59 UTC (4+ messages)
[PATCH v2] fs: clean up usage of noop_dirty_folio
2023-08-28 14:42 UTC (5+ messages)
[PATCH] fs: clean up usage of noop_dirty_folio
2023-08-28 6:36 UTC (4+ messages)
[CXL DAX Question]: How to change the memory-type/cache policy?
2023-08-27 16:43 UTC
[PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling
2023-08-25 14:32 UTC (6+ messages)
` [PATCH v8 03/14] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
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