messages from 2025-08-26 13:18:29 to 2025-09-05 16:12:56 UTC [more...]
[PATCH v3 0/2] FM-API Physical Switch Command Set Support
2025-09-05 16:12 UTC (6+ messages)
` [PATCH v3 1/2] hw/cxl: Refactored Identify Switch Device & Get Physical Port State
` [PATCH v3 2/2] hw/cxl: Add Physical Port Control (Opcode 5102h)
[QEMU- PATCH 0/1] cxl_type3: segfault in cxl_destroy_dc_regions
2025-09-05 14:54 UTC (3+ messages)
` [QEMU- PATCH 1/1] cxl_type3: fix "
[PATCH] acpi, tables: Rename coherency CFMW restrictions
2025-09-05 14:30 UTC (4+ messages)
[PATCH V2 00/20] Add CXL LSA 2.1 format support in nvdimm and cxl pmem
2025-09-05 5:34 UTC (66+ messages)
` [PATCH V2 01/20] nvdimm/label: Introduce NDD_CXL_LABEL flag to set cxl label format
` [PATCH V2 02/20] nvdimm/label: Prep patch to accommodate cxl lsa 2.1 support
` [PATCH V2 03/20] nvdimm/namespace_label: Add namespace label changes as per CXL LSA v2.1
` [PATCH V2 04/20] nvdimm/label: CXL labels skip the need for 'interleave-set cookie'
` [PATCH V2 05/20] nvdimm/region_label: Add region label updation routine
` [PATCH V2 06/20] nvdimm/region_label: Add region label deletion routine
` [PATCH V2 07/20] nvdimm/namespace_label: Update namespace init_labels and its region_uuid
` [PATCH V2 08/20] nvdimm/label: Include region label in slot validation
` [PATCH V2 09/20] nvdimm/namespace_label: Skip region label during ns label DPA reservation
` [PATCH V2 10/20] nvdimm/region_label: Preserve cxl region information from region label
` [PATCH V2 12/20] nvdimm/namespace_label: Skip region label during namespace creation
` [PATCH V2 13/20] cxl/mem: Refactor cxl pmem region auto-assembling
` [PATCH V2 14/20] cxl/region: Add devm_cxl_pmem_add_region() for pmem region creation
[PATCH 0/4 v4] cxl/core: Enable Region creation/attach on x86 with LMH
2025-09-05 0:31 UTC (4+ messages)
` [PATCH 1/4 v4] cxl/core: Change match_*_by_range() signatures
[ndctl PATCH v2] cxl: Add cxl-translate.sh unit test
2025-09-04 23:33 UTC (2+ messages)
[PATCH v2 0/3] CXL: Add a loadable module for address translation
2025-09-04 23:24 UTC (7+ messages)
` [PATCH v2 1/3] cxl/region: Refactor address translation funcs for testing
` [PATCH v2 2/3] cxl/acpi: Make the XOR calculations available "
` [PATCH v2 3/3] cxl/test: Add cxl_translate module for address translation testing
[PATCH v2] cleanup: Fix "unused function" warnings with conditional guards
2025-09-04 22:50 UTC
[PATCH 0/6] dax/hmem, cxl: Coordinate Soft Reserved handling with CXL
2025-09-04 18:14 UTC (16+ messages)
` [PATCH 1/6] dax/hmem, e820, resource: Defer Soft Reserved registration until hmem is ready
` [PATCH 2/6] dax/hmem: Request cxl_acpi and cxl_pci before walking Soft Reserved ranges
` [PATCH 3/6] dax/hmem, cxl: Tighten dependencies on DEV_DAX_CXL and dax_hmem
` [PATCH 4/6] dax/hmem: Defer Soft Reserved overlap handling until CXL region assembly completes
` [PATCH 5/6] dax/hmem: Reintroduce Soft Reserved ranges back into the iomem tree
` [RFC PATCH 6/6] cxl/region, dax/hmem: Guard CXL DAX region creation and tighten HMEM deps
[PATCH v17 00/22] Type2 device basic support
2025-09-04 17:48 UTC (14+ messages)
` [PATCH v17 12/22] sfc: get endpoint decoder
` [PATCH v17 15/22] cxl: Make region type based on endpoint type
` [PATCH v17 19/22] cxl: Avoid dax creation for accelerators
` [PATCH v17 22/22] sfc: support pio mapping based on cxl
[PATCH v8 00/14] Enabling DCD emulation support in Qemu
2025-09-04 8:44 UTC (5+ messages)
` [PATCH v8 11/14] hw/cxl/events: Add qmp interfaces to add/release dynamic capacity extents
[PATCH v11 00/23] Enable CXL PCIe Port Protocol Error handling and logging
2025-09-03 23:23 UTC (53+ messages)
` [PATCH v11 01/23] cxl: Remove ifdef blocks of CONFIG_PCIEAER_CXL from core/pci.c
` [PATCH v11 02/23] CXL/AER: Remove CONFIG_PCIEAER_CXL and replace with CONFIG_CXL_RAS
` [PATCH v11 03/23] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions
` [PATCH v11 04/23] cxl/pci: Remove unnecessary CXL RCH "
` [PATCH v11 05/23] cxl: Move CXL driver RCH error handling into CONFIG_CXL_RCH_RAS conditional block
` [PATCH v11 06/23] CXL/AER: Introduce rch_aer.c into AER driver for handling CXL RCH errors
` [PATCH v11 07/23] CXL/PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h
` [PATCH v11 08/23] PCI/CXL: Introduce pcie_is_cxl()
` [PATCH v11 09/23] PCI/AER: Report CXL or PCIe bus error type in trace logging
` [PATCH v11 10/23] CXL/AER: Update PCI class code check to use FIELD_GET()
` [PATCH v11 11/23] cxl/pci: Update RAS handler interfaces to also support CXL Ports
` [PATCH v11 12/23] cxl/pci: Log message if RAS registers are unmapped
` [PATCH v11 13/23] cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports
` [PATCH v11 14/23] cxl/pci: Update cxl_handle_cor_ras() to return early if no RAS errors
` [PATCH v11 15/23] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers
` [PATCH v11 16/23] cxl/pci: Introduce CXL Endpoint protocol error handlers
` [PATCH v11 17/23] CXL/AER: Introduce cxl_aer.c into AER driver for forwarding CXL errors
` [PATCH v11 18/23] PCI/AER: Dequeue forwarded CXL error
` [PATCH v11 19/23] CXL/PCI: Introduce CXL Port protocol error handlers
` [PATCH v11 20/23] CXL/PCI: Export and rename merge_result() to pci_ers_merge_result()
` [PATCH v11 21/23] CXL/PCI: Introduce CXL uncorrectable protocol error recovery
` [PATCH v11 22/23] CXL/PCI: Enable CXL protocol errors during CXL Port probe
` [PATCH v11 23/23] CXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup
[PATCH v5] cxl: docs/driver-api/conventions resolve conflicts between CFMWS, Low memory Holes, Decoders
2025-09-03 22:05 UTC (3+ messages)
[PATCH v8 00/11] cxl: Delay HB port and switch dport probing until endpoint dev probe
2025-09-03 18:21 UTC (17+ messages)
` [PATCH v8 05/11] cxl: Defer dport allocation for switch ports
[PATCH v3 0/8] Cache coherency management subsystem
2025-09-03 16:25 UTC (5+ messages)
` [PATCH v3 3/8] lib: Support ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION
` [PATCH v3 5/8] arm64: Select GENERIC_CPU_CACHE_MAINTENANCE and ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION
[cxl:next] BUILD SUCCESS 02f6c6a3654911e286ae04e5dfd5deb0f39559b1
2025-09-03 12:38 UTC
[PATCH v3 0/4] cxl, acpi/hmat, node: Update CXL access coordinates to node directly
2025-09-02 23:16 UTC (7+ messages)
` [PATCH v3 1/4] mm/memory_hotplug: Update comment for hotplug memory callback priorities
` [PATCH v3 2/4] drivers/base/node: Add a helper function node_update_perf_attrs()
` [PATCH v3 3/4] cxl, acpi/hmat: Update CXL access coordinates directly instead of through HMAT
` [PATCH v3 4/4] acpi/hmat: Remove now unused hmat_update_target_coordinates()
[PATCH v4] cxl: docs/driver-api/conventions resolve conflicts between CFMWS, LMH, Decoders
2025-09-01 15:23 UTC (6+ messages)
[PATCH v5 0/7] Add managed SOFT RESERVE resource handling
2025-09-01 2:46 UTC (12+ messages)
` [PATCH v5 3/7] cxl/acpi: Add background worker to coordinate with cxl_mem probe completion
[PATCH] Documentation/driver-api: Fix typo error in cxl
2025-08-31 23:07 UTC (3+ messages)
[PATCH v5 2/2] PCI/AER: Print UNCOR_STATUS bits that might be ANFE
2025-08-29 21:18 UTC (2+ messages)
[ndctl PATCH] cxl: Add cxl-translate.sh unit test
2025-08-29 20:32 UTC (5+ messages)
[PATCH v9 00/10] cxl: Delay HB port and switch dport probing until endpoint dev probe
2025-08-29 18:09 UTC (11+ messages)
` [PATCH v9 01/10] cxl: Add helper to detect top of CXL device topology
` [PATCH v9 02/10] cxl: Add helper to reap dport
` [PATCH v9 03/10] cxl: Add a cached copy of target_map to cxl_decoder
` [PATCH v9 04/10] cxl: Move port register setup to first dport appear
` [PATCH v9 05/10] cxl/test: Refactor decoder setup to reduce cxl_test burden
` [PATCH v9 06/10] cxl: Defer dport allocation for switch ports
` [PATCH v9 07/10] cxl/test: Add mock version of devm_cxl_add_dport_by_dev()
` [PATCH v9 08/10] cxl/test: Adjust the mock version of devm_cxl_switch_port_decoders_setup()
` [PATCH v9 09/10] cxl/test: Setup target_map for cxl_test decoder initialization
` [PATCH v9 10/10] cxl: Change sslbis handler to only handle single dport
[PATCH v2 0/4] cxl, acpi/hmat, node: Update CXL access coordinates to node directly
2025-08-29 15:15 UTC (6+ messages)
` [PATCH v2 1/4] mm/memory_hotplug: Update comment for hotplug memory callback priorities
` [PATCH v2 3/4] cxl, acpi/hmat: Update CXL access coordinates directly instead of through HMAT
[PATCH 0/3] CXL: Add a loadable module for address translation
2025-08-29 6:39 UTC (14+ messages)
` [PATCH 1/3] cxl/region: Refactor address translation funcs for testing
` [PATCH 2/3] cxl/acpi: Make the XOR calculations available "
` [PATCH 3/3] cxl/test: Add cxl_translate module for address translation testing
[PATCH v3 0/2] libnvdimm/e820: Add a new parameter to configure many regions per e820 entry
2025-08-29 2:40 UTC (6+ messages)
[PATCH v5 0/2] PCI/AER: Handle Advisory Non-Fatal error
2025-08-28 1:00 UTC (4+ messages)
[PATCH 00/19] perf: Rework event_init checks
2025-08-27 15:15 UTC (26+ messages)
` [PATCH 02/19] perf/hisilicon: Fix group validation
` [PATCH 12/19] perf: Ignore event state for "
` [PATCH 16/19] perf: Introduce positive capability for sampling
` [PATCH 18/19] perf: Introduce positive capability for raw events
[NDCTL PATCH v2] cxl: Add helper function to verify port is in memdev hierarchy
2025-08-27 1:06 UTC (2+ messages)
How to programmatically discover online and offline memory and its latency and bandwidth from user space?
2025-08-26 17:31 UTC (5+ messages)
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