messages from 2026-11-04 23:55:06 to 2026-11-10 04:20:11 UTC [more...]
[PATCH v6 00/25] lib: Rust implementation of SPDM
2026-11-10 4:18 UTC (11+ messages)
` [PATCH v6 01/25] virt: coco: change tsm_register() to use a const struct
` [PATCH v6 02/25] rust: create basic untrusted data API
` [PATCH v6 03/25] rust: validate: add `Validate` trait
` [PATCH v6 04/25] X.509: Make certificate parser public
` [PATCH v6 05/25] X.509: Parse Subject Alternative Name in certificates
` [PATCH v6 06/25] X.509: Move certificate length retrieval into new helper
` [PATCH v6 07/25] rust: add bindings for hash.h
` [PATCH v6 08/25] rust: device: Expose Device as_raw() publicly
` [PATCH v6 09/25] lib: rspdm: Initial commit of Rust SPDM
` [PATCH v6 10/25] PCI/TSM: Rename pf0 to host
[PATCH] MAINTAINERS: Update CXL, NVDIMM, DAX, and others for djbw
2026-11-10 3:54 UTC (2+ messages)
[PATCH] MAINTAINERS: Add CXL reviewer Ben Cheatham
2026-11-10 3:52 UTC (3+ messages)
[PATCH] mm/memory_hotplug: don't offline a hwpoisoned page still in the page cache
2026-11-10 0:27 UTC (5+ messages)
[PATCH v11 00/10] cxl: Support Back-Invalidate
2026-11-09 23:04 UTC (12+ messages)
` [PATCH v11 01/10] cxl: Add BI register probing and port initialization
` [PATCH v11 02/10] cxl/pci: Add BI topology enable/disable
` [PATCH v11 03/10] cxl/hdm: Add BI coherency support for endpoint decoders
` [PATCH v11 04/10] cxl: Add HDM-DB region creation
` [PATCH v11 05/10] cxl/hdm: Rename decoder coherency flags
` [PATCH v11 06/10] cxl/region: Log the coherency model at region creation
` [PATCH v11 07/10] cxl/pci: Split BI capability probe from setup
` [PATCH v11 08/10] cxl: Handle auto-committed BI hdm decoders
` [PATCH v11 09/10] cxl/test: Add mock BI topology support
` [PATCH v11 10/10] cxl/doc: Update maturity map with BI support
[Invitation] Linux MM Alignment Session on Private Nodes and CRAM on Wednesday
2026-11-09 17:03 UTC
[PATCH v2] cxl/region: Restore a target's position from its slot after sorting
2026-11-09 16:43 UTC (2+ messages)
[PATCH v3 00/47] mm: various (urgent?) fixes
2026-11-09 12:47 UTC (10+ messages)
` [PATCH v3 09/47] mm/rmap: handle device-exclusive entries in folio_referenced_one()
` [PATCH v3 18/47] mm/khugepaged: check if PTE table is empty in try_collapse_pte_mapped_thp()
[PATCH] x86/mm: Tear down the direct map when memory hot add fails
2026-11-09 11:52 UTC (6+ messages)
[PATCH v2] dax/pmem: fix unaligned compound devmap initialization
2026-11-09 2:34 UTC (3+ messages)
[PATCH v5 0/3] cxl/edac: Fix event record lookups for memory repair
2026-11-08 2:20 UTC (4+ messages)
` [PATCH v5 1/3] cxl/edac: Read cached DRAM event records under the xarray lock
` [PATCH v5 2/3] cxl/edac: Skip event records marked NOT_REPAIRABLE
` [PATCH v5 3/3] cxl/edac: Mask DPA flags in the event record cache key
[PATCH RFC 0/7] QEMU/hw/cxl: Allow CXL Type 3 memory regions to be initialized at guest boot
2026-11-07 18:39 UTC (6+ messages)
[RFC PATCH 0/5] cxl, mm: Keep device-reported poison out of the page allocator
2026-11-07 15:32 UTC (4+ messages)
` [RFC PATCH 4/5] mm/page_alloc: Keep pre-online poison out of the buddy allocator
[cxl:next] BUILD SUCCESS e44dc3a3037346354ac0dcd70415a7e049fab059
2026-11-07 11:30 UTC
[PATCH 6.18.y] cxl/features: Ensure that count is set before access to ent[] __counted_by()
2026-11-07 7:28 UTC
[PATCH v7 0/5] CXL: Support region granularities finer than the root
2026-11-07 0:59 UTC (8+ messages)
` [PATCH v7 1/5] Documentation/cxl: Describe region granularity "
` [PATCH v7 2/5] cxl/region: Generalize endpoint position mapping
` [PATCH v7 3/5] cxl/region: Support auto region granularity finer than the root
` [PATCH v7 4/5] cxl/region: Support user "
` [PATCH v7 5/5] cxl/test: Add a topology for "
[PATCH v2] cxl/acpi: Drop the root decoder target_type assignment
2026-11-07 0:55 UTC (2+ messages)
[PATCH 0/3] cxl/region: Carry the effective interleave state through target setup
2026-11-07 0:35 UTC (4+ messages)
` [PATCH 1/3] "
` [PATCH 2/3] cxl/test: Add a 2-way 16K root decoder for passthrough testing
` [PATCH 3/3] cxl/test: Program a don't-care granularity into the passthrough host bridge
[PATCH v2 1/2] cxl/mbox: Return success for CXL_MBOX_CMD_RC_BACKGROUND
2026-11-06 23:54 UTC (5+ messages)
` [PATCH v2 2/2] cxl/mbox: Use mapped errno to determine command status
[PATCH v6 00/31] vfio/pci: Add CXL Type-2 device passthrough support
2026-11-06 23:44 UTC (23+ messages)
` [PATCH v6 04/31] PCI/CXL: Let the driver that owns the HDM range run CXL Reset
` [PATCH v6 05/31] PCI: Refuse bus and slot reset below a CXL port with SBR masked
` [PATCH v6 06/31] vfio/pci: Add the CXL provider ops registration interface
` [PATCH v6 07/31] vfio/pci: Detect CXL devices and load the CXL provider on demand
` [PATCH v6 08/31] vfio/pci: Add a generic excluded-range list
` [PATCH v6 09/31] vfio/pci: Advertise the mmap areas around excluded ranges
` [PATCH v6 10/31] vfio/pci: Refuse ioeventfds and dma-buf exports over "
` [PATCH v6 11/31] vfio/pci: Virtualize the CXL DVSEC in vfio_pci_config.c
` [PATCH v6 12/31] vfio/pci: Call the CXL open and close hooks around device use
` [PATCH v6 13/31] vfio/pci: Bracket PCI resets with the CXL reset hooks
` [PATCH v6 15/31] vfio/pci: Route every reset point through a try-reset helper
[PATCH] cxl/test: Free the decoder registry when cxl_test_init() fails
2026-11-06 22:22 UTC
[PATCH v2] mm/memory_hotplug: don't offline a hwpoisoned page still in the page cache
2026-11-06 20:58 UTC (3+ messages)
[PATCH] cxl/region: Restore a target's position from its slot after sorting
2026-11-06 20:28 UTC (2+ messages)
[PATCH v2 0/2] PCI/CXL: Guard MMIO accesses during reset recovery
2026-11-06 18:30 UTC (6+ messages)
` [PATCH v2 1/2] PCI/MSI: Skip MSI-X restoration when configuration is inaccessible
` [PATCH v2 2/2] cxl/pci: Guard decoder accesses after reset
[PATCH 0/4] cxl/region: Update and test performance calculations
2026-11-06 18:25 UTC (10+ messages)
` [PATCH 1/4] cxl/region: Calculate performance data once all targets are attached
` [PATCH 2/4] cxl/region: Show access attributes once performance data is calculated
` [PATCH 3/4] cxl/region: Consolidate region performance completion
` [PATCH 4/4] cxl/test: Give each mock memdev its own performance data
[ndctl PATCH] test/cxl-destroy-region.sh: create RAM regions explicitly
2026-11-06 17:47 UTC (4+ messages)
[PATCH] EINJ, CXL: Use PCI domain for CXL root port error injection
2026-11-06 17:29 UTC (2+ messages)
[PATCH v3 0/3] cxl/test: mock fixups and new topology support
2026-11-06 16:34 UTC (5+ messages)
` [PATCH v3 1/3] tools/testing/cxl: Preserve DPA skip across mock decoder reset
` [PATCH v3 2/3] tools/testing/cxl: Skip the auto region when no volatile window is active
` [PATCH v3 3/3] tools/testing/cxl: Add CFMWS windows for region selection tests
[RFC PATCH v2 0/5] PCI/TSM: Resolve TDISP coherent (CXL) ranges from precommitted HDM decoders
2026-11-06 14:26 UTC (12+ messages)
` [RFC PATCH v2 1/5] PCI/TSM: Create MMIO descriptors via TDISP Report
` [RFC PATCH v2 2/5] PCI/CXL: Populate and insert/remove pdev->coh_resource[]
` [RFC PATCH v2 3/5] PCI/TSM: Derive the coherent-range IPA from CXL
` [RFC PATCH v2 4/5] PCI/TSM: Support multiple coherent ranges via coh_idx
` [RFC PATCH v2 5/5] cxl: Invalidate cached coherent range when Normalized Addressing is detected
[PATCH] mm: split out memory-failure declarations from internal.h
2026-11-06 10:13 UTC (4+ messages)
[RFC PATCH v2 0/3] cxl: Provide explicit RAM region creation for Type-2 providers
2026-11-06 6:25 UTC (4+ messages)
` [RFC PATCH v2 1/3] cxl/mem: Separate provider registration from region attachment
[RFC 00/18] hw/cxl: Add a CXL Type-2 device
2026-11-06 3:59 UTC (19+ messages)
` [RFC 01/18] hw/cxl: Give the component register .io sub-region read-0 ops
` [RFC 02/18] hw/cxl: Factor out cxl_host_addr_to_dpa()
` [RFC 03/18] hw/cxl: Introduce cxl_component_update_dvsec()
` [RFC 04/18] hw/cxl: Make HDM decoder initialization count-aware
` [RFC 05/18] hw/cxl: Define the CXL Device DVSEC capability and control bits
` [RFC 06/18] hw/cxl: Find the memory of a CXL device through one helper
` [RFC 07/18] hw/pci: Add PCI IDs for the CXL Type-2 device
` [RFC 08/18] hw/cxl: Introduce CXL type-2 device emulation
` [RFC 09/18] hw/cxl: Add the CXL type-2 DVSECs and component registers
` [RFC 10/18] hw/cxl: Map the CXL type-2 device memory through the fixed windows
` [RFC 11/18] hw/mem: Require a CXL root port of a pxb-cxl for cxl-type2
` [RFC 12/18] hw/pci-bridge: Add firmware HDM decoder state to pxb-cxl
` [RFC 13/18] hw/mem: Bind cxl-type2 to a fixed memory window
` [RFC 14/18] hw/mem: Commit the cxl-type2 HDM decoder at reset
` [RFC 15/18] hw/mem: Add CXL.cache with cache write-back and invalidate to cxl-type2
` [RFC 16/18] hw/mem: Implement CXL Reset for cxl-type2
` [RFC 17/18] hw/mem: Clear the cxl-type2 volatile memory on a CXL Reset request
` [RFC 18/18] docs/cxl: Document the CXL Type-2 device
[PATCH] dax/pmem: fix unaligned compound devmap initialization
2026-11-06 3:22 UTC (3+ messages)
[ndctl PATCH v2 0/4] libdaxctl: Fix multi-range memory block handling
2026-11-05 21:59 UTC (2+ messages)
[PATCH v17 00/19] PCI/CXL: Add CXL reset support for Type 2 devices
2026-11-05 19:56 UTC (29+ messages)
` [PATCH v17 01/19] cxl: Clarify decoder interleave limit
` [PATCH v17 02/19] cxl: Share CXL port upstream PCI device lookup
` [PATCH v17 03/19] cxl: Move decoder declarations to shared header
` [PATCH v17 04/19] cxl: Embed decoder configuration in a standalone structure
` [PATCH v17 05/19] cxl: Introduce endpoint HDM decoder settings
` [PATCH v17 06/19] cxl: Move HDM decoder helpers to built-in code
` [PATCH v17 07/19] cxl: Share HDM decoder register unpacking
` [PATCH v17 08/19] cxl: Move cxl_rwsem into built-in code
` [PATCH v17 09/19] cxl: Refresh cached PCI HDM decoder settings
` [PATCH v17 10/19] cxl: Build register block helpers into the kernel
` [PATCH v17 11/19] PCI/CXL: Cache endpoint HDM state during PCI enumeration
` [PATCH v17 12/19] PCI/CXL: Add CXL Device Reset sequencing
` [PATCH v17 13/19] cxl: Validate and synchronize HDM ranges around reset
` [PATCH v17 14/19] PCI/CXL: Reject reset with unsafe function scope
` [PATCH v17 15/19] PCI/CXL: Restore CXL state after PCI reset
` [PATCH v17 16/19] PCI/CXL: Expose CXL Reset as a PCI reset method
` [PATCH v17 17/19] PCI/CXL: Restore CXL state after CXL bus reset
` [PATCH v17 18/19] PCI/CXL: Flush host and device caches for "
` [PATCH v17 19/19] cxl: Add KUnit checks for HDM decoder unpacking
[PATCH v15 00/16] PCI/CXL: Add CXL reset support for Type 2 devices
2026-11-05 19:13 UTC (5+ messages)
` [PATCH v15 11/16] cxl: Validate and synchronize HDM ranges around reset
[PATCH v16 00/18] PCI/CXL: Add CXL reset support for Type 2 devices
2026-11-05 19:09 UTC (23+ messages)
` [PATCH v16 07/18] cxl: Share HDM decoder register unpacking
` [PATCH v16 11/18] PCI/CXL: Cache endpoint HDM state during PCI enumeration
` [PATCH v16 12/18] PCI/CXL: Add CXL Device Reset sequencing
` [PATCH v16 13/18] cxl: Validate and synchronize HDM ranges around reset
` [PATCH v16 14/18] PCI/CXL: Reject reset with unsafe function scope
` [PATCH v16 17/18] PCI/CXL: Restore CXL state after CXL bus reset
[PATCH v4 0/2] cxl/edac: Fix event record lookups for memory repair
2026-11-05 8:42 UTC (9+ messages)
` [PATCH v4 1/2] cxl/edac: Read cached DRAM event records under the xarray lock
` [PATCH v4 2/2] cxl/edac: Mask DPA flags in the event record cache key
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