Re: [PATCH v5 0/3] CXL XOR Interleave Arithmetic

[Alison Schofield <alison.schofield@intel.com>]

On Wed, Oct 26, 2022 at 09:07:40PM -0700, alison.schofield@intel.com wrote:
> From: Alison Schofield <alison.schofield@intel.com>
> 
> Changes in v5:

  - Rebase to 6.1-rc2

> - Add to 'n' for 6 & 12 way. (v3->v4 broke it)
> - Clean up x3 index init. (Dan)
> - Remove unneeded HB's from cxl_test topology.
> - Remove dependency on stale patch in cxl_test.
> 
> Changes in v4:
> - Use GENMASK_ULL to fix i386 arch build (0-day)
> - Use do_div to fix ARM arch build (0-day)
> - Update comments in ACPICA patch to reflect new state of the
>   ACPICA patch - pending again in github.
> 
> Changes in v3:
> - Fix the 3, 6, 12 way interleave (again).
> - Do not look for a CXIMS when not needed for x1 & x3 interleaves
> - New cxl_test patch: Add cxl_test module support for this feature
> - In a separate ndctl patch, cxl test: cxl_xor_region is added
> 
> Changes in v2:
> - Use ilog2() of the decoded interleave ways to determine number
>   of xormaps, instead of using encoded ways directly. This fixes
>   3, 6, and 12 way interleaves. (Dan)
> 
> Add support for the new 'XOR' Interleave Arithmetic as defined
> in the CXL 3.0 Specification:
> https://www.computeexpresslink.org/download-the-specification
> 
> 
> Alison Schofield (2):
>   For ACPICA: Add the CXIMS structure definition to the CEDT table
>   cxl/acpi: Support CXL XOR Interleave Math (CXIMS)
>   tools/testing/cxl: Add XOR Math support to cxl_test
> 
>  drivers/cxl/acpi.c           | 129 +++++++++++++++++++++++++++++++++--
>  drivers/cxl/cxl.h            |   2 +
>  include/acpi/actbl1.h        |  14 +++-
>  tools/testing/cxl/test/cxl.c | 118 +++++++++++++++++++++++++++++++-
>  4 files changed, 254 insertions(+), 9 deletions(-)
> 
> -- 
> 2.37.3
>