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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6d451b244fdsm13515096d6.77.2024.11.22.11.46.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Nov 2024 11:46:41 -0800 (PST) Date: Fri, 22 Nov 2024 14:46:31 -0500 From: Gregory Price To: "Fabio M. De Francesco" Cc: Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Huang Ying , Yao Xingtao , Li Ming , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, rrichter@amd.com, terry.bowman@amd.com Subject: Re: [PATCH 0/3] cxl/core: Enable Region creation on x86 with Low Mem Hole Message-ID: References: <20241122155226.2068287-1-fabio.m.de.francesco@linux.intel.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241122155226.2068287-1-fabio.m.de.francesco@linux.intel.com> On Fri, Nov 22, 2024 at 04:51:51PM +0100, Fabio M. De Francesco wrote: > The CXL Fixed Memory Window Structure (CFMWS) describes zero or more Host > Physical Address (HPA) windows that are associated with each CXL Host > Bridge. Each window represents a contiguous HPA that may be interleaved > with one or more targets (CXL v3.1 - 9.18.1.3). > > The Low Memory Hole (LMH) of x86 is a range of addresses of physical low > memory to which systems cannot send transactions. On those systems, BIOS > publishes CFMWS which communicate the active System Physical Address (SPA) > ranges that map to a subset of the Host Physical Address (HPA) ranges. The > SPA range trims out the hole, and capacity in the endpoint is lost with no > SPA to map to CXL HPA in that hole. > > In the early stages of CXL Regions construction and attach on platforms > with Low Memory Holes, the driver fails and returns an error because it > expects that the CXL Endpoint Decoder range is a subset of the Root > Decoder's. > > Then detect SPA/HPA misalignment and allow CXL Regions construction and > attach if and only if the misalignment is due to x86 Low Memory Holes. +cc Robert Richter and Terry Bowman This is not the only memory-hole possibility. We may need something more robust, rather than optimizing for a single memory hole solution. Robert and Terry may have some additional context here. ~Gregory > > - Patch 1/3 changes the calling conventions of three match_*_by_range() > helpers in preparation of 2/3. > - Patch 2/3 detects x86 LMH and enables CXL Regions construction and > attach by trimming HPA by SPA. > - Patch 3/3 simulates a LMH for running the CXL tests on patched driver. > > Many thanks to Alison, Dan, and Ira for their help and for their reviews > of my RFC on Intel's internal ML. > > Fabio M. De Francesco (3): > cxl/core: Change match_*_by_range() calling convention > cxl/core: Enable Region creation on x86 with Low Memory Hole > cxl/test: Simulate an x86 Low Memory Hole for tests > > drivers/cxl/Kconfig | 5 +++ > drivers/cxl/core/Makefile | 1 + > drivers/cxl/core/lmh.c | 58 ++++++++++++++++++++++++++ > drivers/cxl/core/region.c | 80 ++++++++++++++++++++++++++++-------- > drivers/cxl/cxl.h | 32 +++++++++++++++ > tools/testing/cxl/Kbuild | 1 + > tools/testing/cxl/test/cxl.c | 4 +- > 7 files changed, 161 insertions(+), 20 deletions(-) > create mode 100644 drivers/cxl/core/lmh.c > > -- > 2.46.2 >