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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7b9ac4ef0f6sm1609817885a.123.2025.01.07.08.51.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jan 2025 08:51:25 -0800 (PST) Date: Tue, 7 Jan 2025 11:51:23 -0500 From: Gregory Price To: Robert Richter Cc: Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Cameron , Dave Jiang , Davidlohr Bueso , linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, "Fabio M. De Francesco" , Terry Bowman Subject: Re: [PATCH v1 04/29] cxl/pci: Add comments to cxl_hdm_decode_init() Message-ID: References: <20250107141015.3367194-1-rrichter@amd.com> <20250107141015.3367194-5-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250107141015.3367194-5-rrichter@amd.com> On Tue, Jan 07, 2025 at 03:09:50PM +0100, Robert Richter wrote: > There are various configuration cases of HDM decoder registers causing > different code paths. Add comments to cxl_hdm_decode_init() to better > explain them. > > Signed-off-by: Robert Richter > --- > drivers/cxl/core/pci.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > This addresses some of my prior questions, but I still think this function is worth some extra scrutiny. Reviewed-by: Gregory Price > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index c7050c13f71a..4d2154457efb 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -416,9 +416,17 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, > if (global_ctrl & CXL_HDM_DECODER_ENABLE || (!hdm && info->mem_enabled)) > return devm_cxl_enable_mem(&port->dev, cxlds); > > + /* > + * If the HDM Decoder Capability does not exist and DVSEC was > + * not setup, the DVSEC based emulation cannot be used. > + */ > if (!hdm) > return -ENODEV; > > + /* > + * The HDM Decoder Capability exists but is globally disabled. > + */ > + > /* > * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base > * [High,Low] when HDM operation is enabled the range register values > @@ -426,7 +434,8 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, > * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges > * are expected even though Linux does not require or maintain that > * match. If at least one DVSEC range is enabled and allowed, skip HDM > - * Decoder Capability Enable. > + * Decoder Capability Enable. Else, use the HDM Decoder Capability and > + * enable it. > */ > if (!info->mem_enabled) { > rc = devm_cxl_enable_hdm(&port->dev, cxlhdm); > -- > 2.39.5 >