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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6dd181a7c1fsm188506036d6.72.2025.01.07.15.28.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jan 2025 15:28:58 -0800 (PST) Date: Tue, 7 Jan 2025 18:28:57 -0500 From: Gregory Price To: Robert Richter Cc: Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Cameron , Dave Jiang , Davidlohr Bueso , Terry Bowman , linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, "Fabio M. De Francesco" Subject: Re: [PATCH v1 25/29] cxl/amd: Enable Zen5 address translation using ACPI PRMT Message-ID: References: <20250107141015.3367194-1-rrichter@amd.com> <20250107141015.3367194-26-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250107141015.3367194-26-rrichter@amd.com> On Tue, Jan 07, 2025 at 03:10:11PM +0100, Robert Richter wrote: > > Add a function cxl_port_setup_amd() to implement AMD platform specific > code. Use Kbuild and Kconfig options respectivly to enable the code > depending on architecture and platform options. Create a new file > core/amd.c for this. > A build option here specific to AMD doesn't seem the best. At Meta, we try to maintain a platform agnostic kernel for our fleet (at least for build options), and this would necessitate us maintaining separate builds for AMD systems vs other vendors. Is there a reason to simply not include it by default and just report whether translation is required or not? (i.e. no build option) Or maybe generalize to CXL_PLATFORM_QUIRKS rather than CXL_AMD? ~Gregory > Introduce a function cxl_zen5_init() to handle Zen5 specific > enablement. Zen5 platforms are detected using the PCIe vendor and > device ID of the corresponding CXL root port. > > Apply cxl_zen5_to_hpa() as cxl_port->to_hpa() callback to Zen5 CXL > host bridges to enable platform specific address translation. > > Use ACPI PRM DPA to SPA translation to determine an endpoint's > interleaving configuration and base address during the early > initialization proces. This is used to determine an endpoint's SPA > range. > > Since the PRM translates DPA->SPA, but HPA->SPA is needed, determine > the interleaving config and base address of the endpoint first, then > calculate the SPA based on the given HPA using the address base. > > The config can be determined calling the PRM for specific DPAs > given. Since the interleaving configuration is still unknown, chose > DPAs starting at 0xd20000. This address is factor for all values from > 1 to 8 and thus valid for all possible interleaving configuration. > The resulting SPAs are used to calculate interleaving paramters and > the SPA base address of the endpoint. The maximum granularity (chunk > size) is 16k, minimum is 256. Use the following calculation for a > given DPA: > > ways = hpa_len(SZ_16K) / SZ_16K > gran = (hpa_len(SZ_16K) - hpa_len(SZ_16K - SZ_256) - SZ_256) > / (ways - 1) > pos = (hpa_len(SZ_16K) - ways * SZ_16K) / gran > > Once the endpoint is attached to a region and its SPA range is know, > calling the PRM is no longer needed, the SPA base can be used. > > Signed-off-by: Robert Richter > --- > drivers/cxl/Kconfig | 4 + > drivers/cxl/core/Makefile | 1 + > drivers/cxl/core/amd.c | 227 ++++++++++++++++++++++++++++++++++++++ > drivers/cxl/core/core.h | 6 + > drivers/cxl/core/port.c | 7 ++ > 5 files changed, 245 insertions(+) > create mode 100644 drivers/cxl/core/amd.c > > diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig > index 876469e23f7a..e576028dd983 100644 > --- a/drivers/cxl/Kconfig > +++ b/drivers/cxl/Kconfig > @@ -146,4 +146,8 @@ config CXL_REGION_INVALIDATION_TEST > If unsure, or if this kernel is meant for production environments, > say N. > > +config CXL_AMD > + def_bool y > + depends on AMD_NB > + > endif > diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile > index 9259bcc6773c..dc368e61d281 100644 > --- a/drivers/cxl/core/Makefile > +++ b/drivers/cxl/core/Makefile > @@ -16,3 +16,4 @@ cxl_core-y += pmu.o > cxl_core-y += cdat.o > cxl_core-$(CONFIG_TRACING) += trace.o > cxl_core-$(CONFIG_CXL_REGION) += region.o > +cxl_core-$(CONFIG_CXL_AMD) += amd.o > diff --git a/drivers/cxl/core/amd.c b/drivers/cxl/core/amd.c > new file mode 100644 > index 000000000000..553b7d0caefd > --- /dev/null > +++ b/drivers/cxl/core/amd.c > @@ -0,0 +1,227 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2024 Advanced Micro Devices, Inc. > + */ > + > +#include > +#include > + > +#include "cxlmem.h" > +#include "core.h" > + > +#define PCI_DEVICE_ID_AMD_ZEN5_ROOT 0x153e > + > +static const struct pci_device_id zen5_root_port_ids[] = { > + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_ZEN5_ROOT) }, > + {}, > +}; > + > +static int is_zen5_root_port(struct device *dev, void *unused) > +{ > + if (!dev_is_pci(dev)) > + return 0; > + > + return !!pci_match_id(zen5_root_port_ids, to_pci_dev(dev)); > +} > + > +static bool is_zen5(struct cxl_port *port) > +{ > + if (!IS_ENABLED(CONFIG_ACPI_PRMT)) > + return false; > + > + /* To get the CXL root port, find the CXL host bridge first. */ > + if (is_cxl_root(port) || > + !port->host_bridge || > + !is_cxl_root(to_cxl_port(port->dev.parent))) > + return false; > + > + return !!device_for_each_child(port->host_bridge, NULL, > + is_zen5_root_port); > +} > + > +/* > + * PRM Address Translation - CXL DPA to System Physical Address > + * > + * Reference: > + * > + * AMD Family 1Ah Models 00h–0Fh and Models 10h–1Fh > + * ACPI v6.5 Porting Guide, Publication # 58088 > + */ > + > +static const guid_t prm_cxl_dpa_spa_guid = > + GUID_INIT(0xee41b397, 0x25d4, 0x452c, 0xad, 0x54, 0x48, 0xc6, 0xe3, > + 0x48, 0x0b, 0x94); > + > +struct prm_cxl_dpa_spa_data { > + u64 dpa; > + u8 reserved; > + u8 devfn; > + u8 bus; > + u8 segment; > + void *out; > +} __packed; > + > +static u64 prm_cxl_dpa_spa(struct pci_dev *pci_dev, u64 dpa) > +{ > + struct prm_cxl_dpa_spa_data data; > + u64 spa; > + int rc; > + > + data = (struct prm_cxl_dpa_spa_data) { > + .dpa = dpa, > + .devfn = pci_dev->devfn, > + .bus = pci_dev->bus->number, > + .segment = pci_domain_nr(pci_dev->bus), > + .out = &spa, > + }; > + > + rc = acpi_call_prm_handler(prm_cxl_dpa_spa_guid, &data); > + if (rc) { > + pci_dbg(pci_dev, "failed to get SPA for %#llx: %d\n", dpa, rc); > + return ULLONG_MAX; > + } > + > + pci_dbg(pci_dev, "PRM address translation: DPA -> SPA: %#llx -> %#llx\n", dpa, spa); > + > + return spa; > +} > + > +static u64 cxl_zen5_to_hpa(struct cxl_decoder *cxld, u64 hpa) > +{ > + struct cxl_memdev *cxlmd; > + struct pci_dev *pci_dev; > + struct cxl_port *port; > + u64 dpa, base, spa, spa2, len, len2, offset, granularity; > + int ways, pos; > + > + /* > + * Nothing to do if base is non-zero and Normalized Addressing > + * is disabled. > + */ > + if (cxld->hpa_range.start) > + return hpa; > + > + /* Only translate from endpoint to its parent port. */ > + if (!is_endpoint_decoder(&cxld->dev)) > + return hpa; > + > + if (hpa > cxld->hpa_range.end) { > + dev_dbg(&cxld->dev, "hpa addr %#llx out of range %#llx-%#llx\n", > + hpa, cxld->hpa_range.start, cxld->hpa_range.end); > + return ULLONG_MAX; > + } > + > + /* > + * If the decoder is already attached, the region's base can > + * be used. > + */ > + if (cxld->region) > + return cxld->region->params.res->start + hpa; > + > + port = to_cxl_port(cxld->dev.parent); > + cxlmd = port ? to_cxl_memdev(port->uport_dev) : NULL; > + if (!port || !dev_is_pci(cxlmd->dev.parent)) { > + dev_dbg(&cxld->dev, "No endpoint found: %s, range %#llx-%#llx\n", > + dev_name(cxld->dev.parent), cxld->hpa_range.start, > + cxld->hpa_range.end); > + return ULLONG_MAX; > + } > + pci_dev = to_pci_dev(cxlmd->dev.parent); > + > + /* > + * The PRM translates DPA->SPA, but we need HPA->SPA. > + * Determine the interleaving config first, then calculate the > + * DPA. Maximum granularity (chunk size) is 16k, minimum is > + * 256. Calculated with: > + * > + * ways = hpa_len(SZ_16K) / SZ_16K > + * gran = (hpa_len(SZ_16K) - hpa_len(SZ_16K - SZ_256) - SZ_256) > + * / (ways - 1) > + * pos = (hpa_len(SZ_16K) - ways * SZ_16K) / gran > + */ > + > + /* > + * DPA magic: > + * > + * Position and granularity are unknown yet, use an always > + * valid DPA: > + * > + * 0xd20000 = 13762560 = 16k * 2 * 3 * 2 * 5 * 7 * 2 > + * > + * It is divisible by all positions 1 to 8. The DPA is valid > + * for all positions and granularities. > + */ > +#define DPA_MAGIC 0xd20000 > + base = prm_cxl_dpa_spa(pci_dev, DPA_MAGIC); > + spa = prm_cxl_dpa_spa(pci_dev, DPA_MAGIC + SZ_16K); > + spa2 = prm_cxl_dpa_spa(pci_dev, DPA_MAGIC + SZ_16K - SZ_256); > + > + /* Includes checks to avoid div by zero */ > + if (!base || base == ULLONG_MAX || spa == ULLONG_MAX || > + spa2 == ULLONG_MAX || spa < base + SZ_16K || spa2 <= base || > + (spa > base + SZ_16K && spa - spa2 < SZ_256 * 2)) { > + dev_dbg(&cxld->dev, "Error translating HPA: base %#llx, spa %#llx, spa2 %#llx\n", > + base, spa, spa2); > + return ULLONG_MAX; > + } > + > + len = spa - base; > + len2 = spa2 - base; > + > + /* offset = pos * granularity */ > + if (len == SZ_16K && len2 == SZ_16K - SZ_256) { > + ways = 1; > + offset = 0; > + granularity = 0; > + pos = 0; > + } else { > + ways = len / SZ_16K; > + offset = spa & (SZ_16K - 1); > + granularity = (len - len2 - SZ_256) / (ways - 1); > + pos = offset / granularity; > + } > + > + base = base - DPA_MAGIC * ways - pos * granularity; > + spa = base + hpa; > + > + /* > + * Check SPA using a PRM call for the closest DPA calculated > + * for the HPA. If the HPA matches a different interleaving > + * position other than the decoder's, determine its offset to > + * adjust the SPA. > + */ > + > + dpa = (hpa & ~(granularity * ways - 1)) / ways > + + (hpa & (granularity - 1)); > + offset = hpa & (granularity * ways - 1) & ~(granularity - 1); > + offset -= pos * granularity; > + spa2 = prm_cxl_dpa_spa(pci_dev, dpa) + offset; > + > + dev_dbg(&cxld->dev, > + "address mapping found for %s (dpa -> hpa -> spa): %#llx -> %#llx -> %#llx base: %#llx ways: %d pos: %d granularity: %llu\n", > + pci_name(pci_dev), dpa, hpa, spa, base, ways, pos, granularity); > + > + if (spa != spa2) { > + dev_dbg(&cxld->dev, "SPA calculation failed: %#llx:%#llx\n", > + spa, spa2); > + return ULLONG_MAX; > + } > + > + return spa; > +} > + > +static void cxl_zen5_init(struct cxl_port *port) > +{ > + if (!is_zen5(port)) > + return; > + > + port->to_hpa = cxl_zen5_to_hpa; > + > + dev_dbg(port->host_bridge, "PRM address translation enabled for %s.\n", > + dev_name(&port->dev)); > +} > + > +void cxl_port_setup_amd(struct cxl_port *port) > +{ > + cxl_zen5_init(port); > +} > diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h > index 800466f96a68..efe34ae6943e 100644 > --- a/drivers/cxl/core/core.h > +++ b/drivers/cxl/core/core.h > @@ -115,4 +115,10 @@ bool cxl_need_node_perf_attrs_update(int nid); > int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port, > struct access_coordinate *c); > > +#ifdef CONFIG_CXL_AMD > +void cxl_port_setup_amd(struct cxl_port *port); > +#else > +static inline void cxl_port_setup_amd(struct cxl_port *port) {}; > +#endif > + > #endif /* __CXL_CORE_H__ */ > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > index 901555bf4b73..c8176265c15c 100644 > --- a/drivers/cxl/core/port.c > +++ b/drivers/cxl/core/port.c > @@ -831,6 +831,11 @@ static void cxl_debugfs_create_dport_dir(struct cxl_dport *dport) > &cxl_einj_inject_fops); > } > > +static void cxl_port_platform_setup(struct cxl_port *port) > +{ > + cxl_port_setup_amd(port); > +} > + > static int cxl_port_add(struct cxl_port *port, > resource_size_t component_reg_phys, > struct cxl_dport *parent_dport) > @@ -868,6 +873,8 @@ static int cxl_port_add(struct cxl_port *port, > return rc; > } > > + cxl_port_platform_setup(port); > + > rc = device_add(dev); > if (rc) > return rc; > -- > 2.39.5 >