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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6dd180eaa0csm192445276d6.5.2025.01.08.07.48.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jan 2025 07:48:25 -0800 (PST) Date: Wed, 8 Jan 2025 10:48:23 -0500 From: Gregory Price To: Robert Richter Cc: Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Cameron , Dave Jiang , Davidlohr Bueso , Terry Bowman , linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, "Fabio M. De Francesco" Subject: Re: [PATCH v1 25/29] cxl/amd: Enable Zen5 address translation using ACPI PRMT Message-ID: References: <20250107141015.3367194-1-rrichter@amd.com> <20250107141015.3367194-26-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250107141015.3367194-26-rrichter@amd.com> On Tue, Jan 07, 2025 at 03:10:11PM +0100, Robert Richter wrote: > Add AMD platform specific Zen5 support for address translation. > ... snip ... > > Once the endpoint is attached to a region and its SPA range is know, > calling the PRM is no longer needed, the SPA base can be used. > > Signed-off-by: Robert Richter One inline question, but not a blocker Reviewed-by: Gregory Price > --- > drivers/cxl/Kconfig | 4 + > drivers/cxl/core/Makefile | 1 + > drivers/cxl/core/amd.c | 227 ++++++++++++++++++++++++++++++++++++++ > drivers/cxl/core/core.h | 6 + > drivers/cxl/core/port.c | 7 ++ > 5 files changed, 245 insertions(+) > create mode 100644 drivers/cxl/core/amd.c > > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > index 901555bf4b73..c8176265c15c 100644 > --- a/drivers/cxl/core/port.c > +++ b/drivers/cxl/core/port.c > @@ -831,6 +831,11 @@ static void cxl_debugfs_create_dport_dir(struct cxl_dport *dport) > &cxl_einj_inject_fops); > } > > +static void cxl_port_platform_setup(struct cxl_port *port) > +{ > + cxl_port_setup_amd(port); > +} > + Assuming this gets expanded (which it may not), should we expect this function to end up like so? static void cxl_port_platform_setup(struct cxl_port *port) { cxl_port_setup_amd(port); cxl_port_setup_intel(port); cxl_port_setup_arm(port); ... etc ... } I suppose this logic has to exist somewhere in some form, just want to make sure this is what we want. Either way, this is easily modifiable, so not a blocker as I said. > static int cxl_port_add(struct cxl_port *port, > resource_size_t component_reg_phys, > struct cxl_dport *parent_dport) > @@ -868,6 +873,8 @@ static int cxl_port_add(struct cxl_port *port, > return rc; > } > > + cxl_port_platform_setup(port); > + > rc = device_add(dev); > if (rc) > return rc; > -- > 2.39.5 >