From: Alison Schofield <alison.schofield@intel.com>
To: Terry Bowman <terry.bowman@amd.com>
Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, nifan.cxl@gmail.com,
dave@stgolabs.net, jonathan.cameron@huawei.com,
dave.jiang@intel.com, vishal.l.verma@intel.com,
dan.j.williams@intel.com, bhelgaas@google.com,
mahesh@linux.ibm.com, ira.weiny@intel.com, oohall@gmail.com,
Benjamin.Cheatham@amd.com, rrichter@amd.com,
nathan.fontenot@amd.com, Smita.KoralahalliChannabasappa@amd.com,
lukas@wunner.de, ming.li@zohomail.com,
PradeepVineshReddy.Kodamati@amd.com
Subject: Re: [PATCH v7 14/17] cxl/pci: Update CXL Port RAS logging to also display PCIe SBDF
Date: Wed, 12 Feb 2025 15:30:45 -0800 [thread overview]
Message-ID: <Z60vJYIJQxJ7Cu9d@aschofie-mobl2.lan> (raw)
In-Reply-To: <20250211192444.2292833-15-terry.bowman@amd.com>
On Tue, Feb 11, 2025 at 01:24:41PM -0600, Terry Bowman wrote:
> CXL RAS errors are currently logged using the associated CXL port's name
> returned from devname(). They are typically named with 'port1', 'port2',
> etc. to indicate the hierarchial location in the CXL topology. But, this
> doesn't clearly indicate the CXL card or slot reporting the error.
>
> Update the logging to also log the corresponding PCIe devname. This will
> give a PCIe SBDF or ACPI object name (in case of CXL HB). This will provide
> details helping users understand which physical slot and card has the
> error.
>
> Below is example output after making these changes.
>
> Correctable error example output:
> cxl_port_aer_correctable_error: device=port1 (0000:0c:00.0) parent=root0 (pci0000:0c) status='Received Error From Physical Layer'
>
> Uncorrectable error example output:
> cxl_port_aer_uncorrectable_error: device=port1 (0000:0c:00.0) parent=root0 (pci0000:0c) status: 'Memory Byte Enable Parity Error' first_error: 'Memory Byte Enable Parity Error'
snip
>
>
> TRACE_EVENT(cxl_port_aer_uncorrectable_error,
> - TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl),
> - TP_ARGS(dev, status, fe, hl),
> + TP_PROTO(struct device *cxl_dev, struct device *pcie_dev, u32 status, u32 fe, u32 *hl),
> + TP_ARGS(cxl_dev, pcie_dev, status, fe, hl),
> TP_STRUCT__entry(
> - __string(devname, dev_name(dev))
> - __string(parent, dev_name(dev->parent))
> + __string(cxl_name, dev_name(cxl_dev))
> + __string(cxl_parent_name, dev_name(cxl_dev->parent))
> + __string(pcie_name, dev_name(pcie_dev))
> + __string(pcie_parent_name, dev_name(pcie_dev->parent))
I get the rename of devname->cxl_name and parent->cxl_parent_name
since now we have pcie names too. How about making those changes
in the previous patch where devname and parent are introduced. Then
this patch doesn't have any changes other than adding the pcie names.
Having said that, should/can this merge with the patch before it?
snip
next prev parent reply other threads:[~2025-02-12 23:30 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-11 19:24 [PATCH v7 00/17] Enable CXL PCIe port protocol error handling and logging Terry Bowman
2025-02-11 19:24 ` [PATCH v7 01/17] PCI/AER: Introduce 'struct cxl_err_handlers' and add to 'struct pci_driver' Terry Bowman
2025-02-11 20:25 ` Bjorn Helgaas
2025-02-11 20:42 ` Dan Williams
2025-02-11 19:24 ` [PATCH v7 02/17] PCI/AER: Rename AER driver's interfaces to also indicate CXL PCIe Port support Terry Bowman
2025-02-11 20:26 ` Bjorn Helgaas
2025-02-11 20:44 ` Dan Williams
2025-02-11 19:24 ` [PATCH v7 03/17] CXL/PCI: Introduce PCIe helper functions pcie_is_cxl() and pcie_is_cxl_port() Terry Bowman
2025-02-11 20:28 ` Bjorn Helgaas
2025-02-11 20:38 ` Bowman, Terry
2025-02-11 22:33 ` Dan Williams
2025-02-12 19:07 ` Bowman, Terry
2025-02-12 19:51 ` Dan Williams
2025-03-04 19:11 ` Ira Weiny
2025-02-11 19:24 ` [PATCH v7 04/17] PCI/AER: Modify AER driver logging to report CXL or PCIe bus error type Terry Bowman
2025-02-11 20:28 ` Bjorn Helgaas
2025-02-11 23:47 ` Dan Williams
2025-02-12 19:15 ` Bowman, Terry
2025-02-12 19:57 ` Dan Williams
2025-02-12 21:08 ` Bowman, Terry
2025-02-12 21:17 ` Lukas Wunner
2025-02-11 19:24 ` [PATCH v7 05/17] PCI/AER: Add CXL PCIe Port correctable error support in AER service driver Terry Bowman
2025-02-11 20:28 ` Bjorn Helgaas
2025-02-11 23:58 ` Dan Williams
2025-02-12 21:52 ` Bowman, Terry
2025-02-11 19:24 ` [PATCH v7 06/17] PCI/AER: Add CXL PCIe Port uncorrectable error recovery " Terry Bowman
2025-02-11 20:29 ` Bjorn Helgaas
2025-02-11 21:59 ` Dave Jiang
2025-02-12 0:02 ` Gregory Price
2025-02-12 0:24 ` Dan Williams
2025-02-14 19:36 ` Bowman, Terry
2025-02-14 15:11 ` Jonathan Cameron
2025-02-18 15:43 ` Bowman, Terry
2025-02-14 17:36 ` Fan Ni
2025-02-11 19:24 ` [PATCH v7 07/17] cxl/pci: Map CXL PCIe Root Port and Downstream Switch Port RAS registers Terry Bowman
2025-02-11 22:40 ` Dave Jiang
2025-02-12 1:23 ` Dan Williams
2025-02-13 15:43 ` Bowman, Terry
2025-02-14 21:24 ` Dan Williams
2025-02-14 22:23 ` Bowman, Terry
2025-02-14 22:42 ` Dan Williams
2025-02-12 22:28 ` Alison Schofield
2025-02-12 22:37 ` Bowman, Terry
2025-02-11 19:24 ` [PATCH v7 08/17] cxl/pci: Map CXL PCIe Upstream " Terry Bowman
2025-02-11 23:02 ` Dave Jiang
2025-02-12 2:00 ` Dan Williams
2025-02-14 19:46 ` Bowman, Terry
2025-02-14 21:29 ` Dan Williams
2025-02-14 15:15 ` Jonathan Cameron
2025-02-14 19:50 ` Bowman, Terry
2025-02-11 19:24 ` [PATCH v7 09/17] cxl/pci: Update RAS handler interfaces to also support CXL PCIe Ports Terry Bowman
2025-02-11 23:26 ` Dave Jiang
2025-02-14 15:19 ` Jonathan Cameron
2025-02-11 19:24 ` [PATCH v7 10/17] cxl/pci: Add log message and add type check in existing RAS handlers Terry Bowman
2025-02-11 23:28 ` Dave Jiang
2025-02-12 22:59 ` Dan Williams
2025-02-13 0:08 ` Bowman, Terry
2025-02-14 15:28 ` Jonathan Cameron
2025-02-11 19:24 ` [PATCH v7 11/17] cxl/pci: Change find_cxl_port() to non-static Terry Bowman
2025-02-11 23:42 ` Dave Jiang
2025-02-13 23:15 ` Dan Williams
2025-02-11 19:24 ` [PATCH v7 12/17] cxl/pci: Add error handler for CXL PCIe Port RAS errors Terry Bowman
2025-02-12 0:11 ` Dave Jiang
2025-02-12 16:34 ` Bowman, Terry
2025-02-14 2:18 ` Dan Williams
2025-02-14 21:43 ` Bowman, Terry
2025-02-15 0:20 ` Dan Williams
2025-02-18 15:33 ` Bowman, Terry
2025-02-18 17:15 ` Dan Williams
2025-03-05 0:22 ` Ira Weiny
2025-03-06 13:50 ` Bowman, Terry
2025-03-06 13:50 ` Bowman, Terry
2025-02-11 19:24 ` [PATCH v7 13/17] cxl/pci: Add trace logging " Terry Bowman
2025-02-12 0:11 ` Gregory Price
2025-02-12 0:17 ` Dave Jiang
2025-02-12 0:19 ` Dave Jiang
2025-02-12 16:23 ` Bowman, Terry
2025-02-14 2:21 ` Dan Williams
2025-02-14 15:34 ` Jonathan Cameron
2025-02-11 19:24 ` [PATCH v7 14/17] cxl/pci: Update CXL Port RAS logging to also display PCIe SBDF Terry Bowman
2025-02-12 0:21 ` Dave Jiang
2025-02-12 16:20 ` Bowman, Terry
2025-02-12 23:30 ` Alison Schofield [this message]
2025-02-12 23:34 ` Bowman, Terry
2025-02-11 19:24 ` [PATCH v7 15/17] cxl/pci: Add support to assign and clear pci_driver::cxl_err_handlers Terry Bowman
2025-02-12 0:38 ` Dave Jiang
2025-02-14 2:29 ` Dan Williams
2025-02-11 19:24 ` [PATCH v7 16/17] PCI/AER: Enable internal errors for CXL Upstream and Downstream Switch Ports Terry Bowman
2025-02-11 20:25 ` Bjorn Helgaas
2025-02-11 20:40 ` Bowman, Terry
2025-02-12 0:40 ` Dave Jiang
2025-02-14 2:35 ` Dan Williams
2025-02-11 19:24 ` [PATCH v7 17/17] cxl/pci: Handle CXL Endpoint and RCH Protocol Errors separately from PCIe errors Terry Bowman
2025-02-14 2:43 ` Dan Williams
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