From: Gregory Price <gourry@gourry.net>
To: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Cc: linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-cxl@vger.kernel.org, Ard Biesheuvel <ardb@kernel.org>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Yazen Ghannam <yazen.ghannam@amd.com>,
Terry Bowman <terry.bowman@amd.com>
Subject: Re: [PATCH v6 6/6] cxl/pci: Add trace logging for CXL PCIe Port RAS errors
Date: Wed, 5 Feb 2025 15:01:57 -0500 [thread overview]
Message-ID: <Z6PDtW0omzmMjjXN@gourry-fedora-PF4VCD3F> (raw)
In-Reply-To: <20250123084421.127697-7-Smita.KoralahalliChannabasappa@amd.com>
On Thu, Jan 23, 2025 at 08:44:21AM +0000, Smita Koralahalli wrote:
> The CXL drivers use kernel trace functions for logging endpoint and
> Restricted CXL host (RCH) Downstream Port RAS errors. Similar functionality
> is required for CXL Root Ports, CXL Downstream Switch Ports, and CXL
> Upstream Switch Ports.
>
> Introduce trace logging functions for both RAS correctable and
> uncorrectable errors specific to CXL PCIe Ports. Use them to trace
> FW-First Protocol errors.
>
> Co-developed-by: Terry Bowman <terry.bowman@amd.com>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Reviewed-by: Gregory Price <gourry@gourry.net>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 9d4b5f39b21a..766447c169c8 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -1168,6 +1168,7 @@ static void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)
> pci_get_domain_bus_and_slot(data->prot_err.agent_addr.segment,
> data->prot_err.agent_addr.bus,
> devfn);
> + int port_type;
>
> if (!pdev)
> return;
> @@ -1176,6 +1177,18 @@ static void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)
> if (pdev->driver != &cxl_pci_driver)
> return;
>
> + port_type = pci_pcie_type(pdev);
> + if (port_type == PCI_EXP_TYPE_ROOT_PORT ||
> + port_type == PCI_EXP_TYPE_DOWNSTREAM ||
> + port_type == PCI_EXP_TYPE_UPSTREAM) {
Almost wish this was a macro for the sake of style, but not worth it.
"corr_prot_err" and "port_prot_err" kind of blend at first glance. Not
worth holding anything up.
> + if (data->severity == AER_CORRECTABLE)
> + cxl_cper_trace_corr_port_prot_err(pdev, data->ras_cap);
> + else
> + cxl_cper_trace_uncorr_port_prot_err(pdev, data->ras_cap);
> +
> + return;
> + }
> +
> if (data->severity == AER_CORRECTABLE)
> cxl_cper_trace_corr_prot_err(pdev, data->ras_cap);
> else
> --
> 2.17.1
>
next prev parent reply other threads:[~2025-02-05 20:02 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-23 8:44 [PATCH v6 0/6] acpi/ghes, cper, cxl: Process CXL CPER Protocol errors Smita Koralahalli
2025-01-23 8:44 ` [PATCH v6 1/6] efi/cper, cxl: Prefix protocol error struct and function names with cxl_ Smita Koralahalli
2025-02-04 0:12 ` Fan Ni
2025-02-05 19:17 ` Gregory Price
2025-01-23 8:44 ` [PATCH v6 2/6] efi/cper, cxl: Make definitions and structures global Smita Koralahalli
2025-02-04 0:16 ` Fan Ni
2025-02-05 19:16 ` Gregory Price
2025-02-06 10:54 ` Jonathan Cameron
2025-02-06 16:14 ` Gregory Price
2025-02-06 17:14 ` Konstantin Ryabitsev
2025-02-06 17:32 ` Gregory Price
2025-01-23 8:44 ` [PATCH v6 3/6] efi/cper, cxl: Remove cper_cxl.h Smita Koralahalli
2025-02-04 0:20 ` Fan Ni
2025-02-05 19:18 ` Gregory Price
2025-01-23 8:44 ` [PATCH v6 4/6] acpi/ghes, cper: Recognize and cache CXL Protocol errors Smita Koralahalli
2025-02-03 18:59 ` Luck, Tony
2025-02-05 19:35 ` Gregory Price
2025-02-05 22:21 ` Dan Williams
2025-07-22 19:24 ` "invalid agent type: 1" in " Marc Herbert
2025-07-23 7:13 ` Marc Herbert
2025-07-24 14:49 ` Fabio M. De Francesco
2025-07-25 11:04 ` Jonathan Cameron
2025-07-28 15:01 ` dan.j.williams
2025-07-28 16:25 ` Koralahalli Channabasappa, Smita
2025-07-29 5:41 ` Marc Herbert
2025-07-29 15:52 ` Koralahalli Channabasappa, Smita
2025-07-29 17:39 ` dan.j.williams
2025-01-23 8:44 ` [PATCH v6 5/6] acpi/ghes, cxl/pci: Process CXL CPER Protocol Errors Smita Koralahalli
2025-02-03 19:03 ` Luck, Tony
2025-02-12 21:04 ` Koralahalli Channabasappa, Smita
2025-02-05 19:50 ` Gregory Price
2025-02-05 22:58 ` Dan Williams
2025-02-12 20:57 ` Koralahalli Channabasappa, Smita
2025-01-23 8:44 ` [PATCH v6 6/6] cxl/pci: Add trace logging for CXL PCIe Port RAS errors Smita Koralahalli
2025-01-24 16:36 ` Ira Weiny
2025-02-05 20:01 ` Gregory Price [this message]
2025-02-05 23:06 ` Dan Williams
2025-02-03 17:09 ` [PATCH v6 0/6] acpi/ghes, cper, cxl: Process CXL CPER Protocol errors Dave Jiang
2025-02-06 18:38 ` Dave Jiang
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