Re: [PATCH v5 3/4] cxl: Add extended linear cache address alias emission for cxl events

[Alison Schofield <alison.schofield@intel.com>]

On Wed, Feb 26, 2025 at 09:21:20AM -0700, Dave Jiang wrote:
> Add the aliased address of extended linear cache when emitting event
> trace for DRAM and general media of CXL events.

and poison events.

> 
snip

> @@ -870,6 +876,7 @@ TRACE_EVENT(cxl_poison,
>  		__string(region, cxlr ? dev_name(&cxlr->dev) : "")
>  		__field(u64, overflow_ts)
>  		__field(u64, hpa)
> +		__field(u64, hpa_alias0)
>  		__field(u64, dpa)
>  		__field(u32, dpa_length)
>  		__array(char, uuid, 16)
> @@ -892,16 +899,19 @@ TRACE_EVENT(cxl_poison,
>  			memcpy(__entry->uuid, &cxlr->params.uuid, 16);
>  			__entry->hpa = cxl_dpa_to_hpa(cxlr, cxlmd,
>  						      __entry->dpa);
> +			__entry->hpa_alias0 = cxlr->params.cache_size ?
> +				__entry->hpa + cxlr->params.cache_size : ULLONG_MAX;

check for cxl_dpa_to_hpa() returning ULLONG_MAX before doing alias math.

>  		} else {
>  			__assign_str(region);
>  			memset(__entry->uuid, 0, 16);
>  			__entry->hpa = ULLONG_MAX;
> +			__entry->hpa_alias0 = ULLONG_MAX;
>  		}
>  	    ),

snip