From: Alison Schofield <alison.schofield@intel.com>
To: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Cc: linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-cxl@vger.kernel.org, Ard Biesheuvel <ardb@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Yazen Ghannam <yazen.ghannam@amd.com>,
Terry Bowman <terry.bowman@amd.com>
Subject: Re: [PATCH v7 2/2] cxl/pci: Add trace logging for CXL PCIe Port RAS errors
Date: Tue, 4 Mar 2025 10:56:51 -0800 [thread overview]
Message-ID: <Z8dM80wy5Q8UQomz@aschofie-mobl2.lan> (raw)
In-Reply-To: <20250226221157.149406-3-Smita.KoralahalliChannabasappa@amd.com>
On Wed, Feb 26, 2025 at 10:11:57PM +0000, Smita Koralahalli wrote:
Kind of a nit, but since these are exposed to user space suggest
matching these names now.
> +++ b/drivers/cxl/core/trace.h
> @@ -48,6 +48,34 @@
> { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \
> )
>
> +TRACE_EVENT(cxl_port_aer_uncorrectable_error,
> + TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl),
> + TP_ARGS(dev, status, fe, hl),
> + TP_STRUCT__entry(
> + __string(devname, dev_name(dev))
> + __string(parent, dev_name(dev->parent))
Above devname, parent
> + __field(u32, status)
> + __field(u32, first_error)
> + __array(u32, header_log, CXL_HEADERLOG_SIZE_U32)
> + ),
> + TP_fast_assign(
> + __assign_str(devname);
> + __assign_str(parent);
> + __entry->status = status;
> + __entry->first_error = fe;
> + /*
> + * Embed the 512B headerlog data for user app retrieval and
> + * parsing, but no need to print this in the trace buffer.
> + */
> + memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);
> + ),
> + TP_printk("device=%s host=%s status: '%s' first_error: '%s'",
Above device, host
> + __get_str(devname), __get_str(parent),
> + show_uc_errs(__entry->status),
> + show_uc_errs(__entry->first_error)
> + )
> +);
> +
> TRACE_EVENT(cxl_aer_uncorrectable_error,
> TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl),
> TP_ARGS(cxlmd, status, fe, hl),
> @@ -96,6 +124,25 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,
> { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \
> )
>
same thing below -
> +TRACE_EVENT(cxl_port_aer_correctable_error,
> + TP_PROTO(struct device *dev, u32 status),
> + TP_ARGS(dev, status),
> + TP_STRUCT__entry(
> + __string(devname, dev_name(dev))
> + __string(parent, dev_name(dev->parent))
> + __field(u32, status)
> + ),
> + TP_fast_assign(
> + __assign_str(devname);
> + __assign_str(parent);
> + __entry->status = status;
> + ),
> + TP_printk("device=%s host=%s status='%s'",
> + __get_str(devname), __get_str(parent),
> + show_ce_errs(__entry->status)
> + )
> +);
> +
> TRACE_EVENT(cxl_aer_correctable_error,
> TP_PROTO(const struct cxl_memdev *cxlmd, u32 status),
> TP_ARGS(cxlmd, status),
> --
> 2.17.1
>
next prev parent reply other threads:[~2025-03-04 18:56 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-26 22:11 [PATCH v7 0/2] acpi/ghes, cper, cxl: Process CXL CPER Protocol errors Smita Koralahalli
2025-02-26 22:11 ` [PATCH v7 1/2] acpi/ghes, cxl/pci: Process CXL CPER Protocol Errors Smita Koralahalli
2025-03-04 17:44 ` Ira Weiny
2025-03-05 0:56 ` Ira Weiny
2025-03-04 19:57 ` Yazen Ghannam
2025-03-04 20:16 ` Koralahalli Channabasappa, Smita
2025-02-26 22:11 ` [PATCH v7 2/2] cxl/pci: Add trace logging for CXL PCIe Port RAS errors Smita Koralahalli
2025-03-04 17:45 ` Ira Weiny
2025-03-04 18:56 ` Alison Schofield [this message]
2025-03-04 20:33 ` Koralahalli Channabasappa, Smita
2025-03-04 21:10 ` Alison Schofield
2025-03-04 21:21 ` Alison Schofield
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