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From: Alison Schofield <alison.schofield@intel.com>
To: Terry Bowman <terry.bowman@amd.com>
Cc: vishal.l.verma@intel.com, ira.weiny@intel.com,
	bwidawsk@kernel.org, dan.j.williams@intel.com,
	dave.jiang@intel.com, Jonathan.Cameron@huawei.com,
	linux-cxl@vger.kernel.org,
	Smita.KoralahalliChannabasappa@amd.com, rrichter@amd.com,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] cxl/pci: Change CXL AER support check to use native AER
Date: Thu, 2 Nov 2023 13:19:55 -0700	[thread overview]
Message-ID: <ZUQEa1q/R2KBF/3W@aschofie-mobl2> (raw)
In-Reply-To: <20231102155232.1421261-1-terry.bowman@amd.com>

On Thu, Nov 02, 2023 at 10:52:32AM -0500, Terry Bowman wrote:
> Native CXL protocol errors are delivered to the OS through AER
> reporting. The owner of AER owns CXL Protocol error management with
> respect to _OSC negotiation.[1] CXL device errors are handled by a
> separate interrupt with native control gated by _OSC control field
> 'CXL Memory Error Reporting Control'.
> 
> The CXL driver incorrectly checks for 'CXL Memory Error Reporting
> Control' before accessing AER registers and caching RCH downport
> AER registers. Replace the current check in these 2 cases with
> native AER checks.

Hi Terry,  Does this have a user visible impact? 

Alison

>
--snip


  reply	other threads:[~2023-11-02 20:20 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-02 15:52 [PATCH] cxl/pci: Change CXL AER support check to use native AER Terry Bowman
2023-11-02 20:19 ` Alison Schofield [this message]
2023-11-02 21:13   ` Dan Williams
2023-11-02 21:31     ` Dan Williams
2023-11-02 23:24       ` Terry Bowman
2023-11-02 21:09 ` Dan Williams

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