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[71.202.32.218]) by smtp.gmail.com with ESMTPSA id ey9-20020a056a0038c900b006d70b0d4639sm14160191pfb.107.2024.01.24.10.09.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 10:09:10 -0800 (PST) From: fan X-Google-Original-From: fan Date: Wed, 24 Jan 2024 10:08:50 -0800 To: Jonathan Cameron Cc: qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, Fan Ni , Michael Tsirkin , Davidlohr Bueso , linuxarm@huawei.com, Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Subject: Re: [PATCH 1/5] hw/cxl: Update HDM Decoder capability to version 3 Message-ID: References: <20240124134814.8717-1-Jonathan.Cameron@huawei.com> <20240124134814.8717-2-Jonathan.Cameron@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240124134814.8717-2-Jonathan.Cameron@huawei.com> On Wed, Jan 24, 2024 at 01:48:10PM +0000, Jonathan Cameron wrote: > Part of standardizing the QEMU code on CXL r3.1. > No fuctional changes as everything added is optional and > it is set as not implemented. > > Signed-off-by: Jonathan Cameron > --- Reviewed-by: Fan Ni > include/hw/cxl/cxl_component.h | 16 ++++++++++++++-- > hw/cxl/cxl-component-utils.c | 10 +++++++++- > 2 files changed, 23 insertions(+), 3 deletions(-) > > diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h > index 5227a8e833..7d3edef1bf 100644 > --- a/include/hw/cxl/cxl_component.h > +++ b/include/hw/cxl/cxl_component.h > @@ -109,8 +109,9 @@ REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18) > (CXL_SEC_REGISTERS_OFFSET + CXL_SEC_REGISTERS_SIZE) > #define CXL_LINK_REGISTERS_SIZE 0x38 > > -/* 8.2.5.12 - CXL HDM Decoder Capability Structure */ > -#define HDM_DECODE_MAX 10 /* 8.2.5.12.1 */ > +/* CXL r3.1 Section 8.2.4.20: CXL HDM Decoder Capability Structure */ > +#define HDM_DECODE_MAX 10 /* Maximum decoders for Devices */ > +#define CXL_HDM_CAPABILITY_VERSION 3 > #define CXL_HDM_REGISTERS_OFFSET \ > (CXL_LINK_REGISTERS_OFFSET + CXL_LINK_REGISTERS_SIZE) > #define CXL_HDM_REGISTERS_SIZE (0x10 + 0x20 * HDM_DECODE_MAX) > @@ -133,6 +134,11 @@ REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18) > FIELD(CXL_HDM_DECODER##n##_CTRL, COMMITTED, 10, 1) \ > FIELD(CXL_HDM_DECODER##n##_CTRL, ERR, 11, 1) \ > FIELD(CXL_HDM_DECODER##n##_CTRL, TYPE, 12, 1) \ > + FIELD(CXL_HDM_DECODER##n##_CTRL, BI, 13, 1) \ > + FIELD(CXL_HDM_DECODER##n##_CTRL, UIO, 14, 1) \ > + FIELD(CXL_HDM_DECODER##n##_CTRL, UIG, 16, 4) \ > + FIELD(CXL_HDM_DECODER##n##_CTRL, UIW, 20, 4) \ > + FIELD(CXL_HDM_DECODER##n##_CTRL, ISP, 24, 4) \ > REG32(CXL_HDM_DECODER##n##_TARGET_LIST_LO, \ > CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x24) \ > REG32(CXL_HDM_DECODER##n##_TARGET_LIST_HI, \ > @@ -148,6 +154,12 @@ REG32(CXL_HDM_DECODER_CAPABILITY, CXL_HDM_REGISTERS_OFFSET) > FIELD(CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 8, 1) > FIELD(CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 9, 1) > FIELD(CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 10, 1) > + FIELD(CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY, 11, 1) > + FIELD(CXL_HDM_DECODER_CAPABILITY, 16_WAY, 12, 1) > + FIELD(CXL_HDM_DECODER_CAPABILITY, UIO, 13, 1) > + FIELD(CXL_HDM_DECODER_CAPABILITY, UIO_DECODER_COUNT, 16, 4) > + FIELD(CXL_HDM_DECODER_CAPABILITY, MEMDATA_NXM_CAP, 20, 1) > + FIELD(CXL_HDM_DECODER_CAPABILITY, SUPPORTED_COHERENCY_MODEL, 21, 2) > REG32(CXL_HDM_DECODER_GLOBAL_CONTROL, CXL_HDM_REGISTERS_OFFSET + 4) > FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, POISON_ON_ERR_EN, 0, 1) > FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, HDM_DECODER_ENABLE, 1, 1) > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c > index 5ddd47ed8d..a55cf5a036 100644 > --- a/hw/cxl/cxl-component-utils.c > +++ b/hw/cxl/cxl-component-utils.c > @@ -243,6 +243,14 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 1); > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, > POISON_ON_ERR_CAP, 0); > + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY, 0); > + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, 16_WAY, 0); > + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, UIO, 0); > + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, > + UIO_DECODER_COUNT, 0); > + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, MEMDATA_NXM_CAP, 0); > + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, > + SUPPORTED_COHERENCY_MODEL, 0); /* Unknown */ > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL, > HDM_DECODER_ENABLE, 0); > write_msk[R_CXL_HDM_DECODER_GLOBAL_CONTROL] = 0x3; > @@ -326,7 +334,7 @@ void cxl_component_register_init_common(uint32_t *reg_state, > return; > } > > - init_cap_reg(HDM, 5, 1); > + init_cap_reg(HDM, 5, CXL_HDM_CAPABILITY_VERSION); > hdm_init_common(reg_state, write_msk, type); > > if (caps < 5) { > -- > 2.39.2 >