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[71.202.32.218]) by smtp.gmail.com with ESMTPSA id u11-20020a170903308b00b001d76e9ce688sm3021216plc.114.2024.01.24.10.20.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 10:20:33 -0800 (PST) From: fan X-Google-Original-From: fan Date: Wed, 24 Jan 2024 10:20:31 -0800 To: Jonathan Cameron Cc: qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, Fan Ni , Michael Tsirkin , Davidlohr Bueso , linuxarm@huawei.com, Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Subject: Re: [PATCH 2/5] hw/cxl: Update link register definitions. Message-ID: References: <20240124134814.8717-1-Jonathan.Cameron@huawei.com> <20240124134814.8717-3-Jonathan.Cameron@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240124134814.8717-3-Jonathan.Cameron@huawei.com> On Wed, Jan 24, 2024 at 01:48:11PM +0000, Jonathan Cameron wrote: > Not actually implemented, but we need to reserve more space for > the larger version of the structure in CXL r3.1. > > Signed-off-by: Jonathan Cameron > --- Reviewed-by: Fan Ni > include/hw/cxl/cxl_component.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h > index 7d3edef1bf..2c7631bd1e 100644 > --- a/include/hw/cxl/cxl_component.h > +++ b/include/hw/cxl/cxl_component.h > @@ -104,10 +104,10 @@ REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18) > (CXL_RAS_REGISTERS_OFFSET + CXL_RAS_REGISTERS_SIZE) > #define CXL_SEC_REGISTERS_SIZE 0 /* We don't implement 1.1 downstream ports */ > > -/* 8.2.5.11 - CXL Link Capability Structure */ > +/* CXL r3.1 Section 8.2.4.19: CXL Link Capability Structure */ > #define CXL_LINK_REGISTERS_OFFSET \ > (CXL_SEC_REGISTERS_OFFSET + CXL_SEC_REGISTERS_SIZE) > -#define CXL_LINK_REGISTERS_SIZE 0x38 > +#define CXL_LINK_REGISTERS_SIZE 0x50 > > /* CXL r3.1 Section 8.2.4.20: CXL HDM Decoder Capability Structure */ > #define HDM_DECODE_MAX 10 /* Maximum decoders for Devices */ > -- > 2.39.2 >