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[71.202.32.218]) by smtp.gmail.com with ESMTPSA id fk19-20020a056a003a9300b006db87354a8fsm14260226pfb.119.2024.01.24.15.46.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 15:46:06 -0800 (PST) From: fan X-Google-Original-From: fan Date: Wed, 24 Jan 2024 15:46:04 -0800 To: Jonathan Cameron Cc: qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, Fan Ni , Michael Tsirkin , Ira Weiny , Huai-Cheng Kuo , Dave Jiang , Peter Maydell , Davidlohr Bueso , Hyeonggon Yoo <42.hyeyoo@gmail.com>, Li Zhijian , Stefan Hajnoczi , linuxarm@huawei.com, Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Subject: Re: [PATCH 07/12] hw/cxl: Pass CXLComponentState to cache_mem_ops Message-ID: References: <20240124124100.8218-1-Jonathan.Cameron@huawei.com> <20240124124100.8218-8-Jonathan.Cameron@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240124124100.8218-8-Jonathan.Cameron@huawei.com> On Wed, Jan 24, 2024 at 12:40:55PM +0000, Jonathan Cameron wrote: > From: Li Zhijian > > cache_mem_ops.{read,write}() interprets opaque as > CXLComponentState(cxl_cstate) instead of ComponentRegisters(cregs). > > Fortunately, cregs is the first member of cxl_cstate, so their values are > the same. > > Fixes: 9e58f52d3f8 ("hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)") > Signed-off-by: Li Zhijian > Signed-off-by: Jonathan Cameron Reviewed-by: Fan Ni > --- > hw/cxl/cxl-component-utils.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c > index 29d477492b..9dfde6c0b3 100644 > --- a/hw/cxl/cxl-component-utils.c > +++ b/hw/cxl/cxl-component-utils.c > @@ -199,7 +199,7 @@ void cxl_component_register_block_init(Object *obj, > /* io registers controls link which we don't care about in QEMU */ > memory_region_init_io(&cregs->io, obj, NULL, cregs, ".io", > CXL2_COMPONENT_IO_REGION_SIZE); > - memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs, > + memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cxl_cstate, > ".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE); > > memory_region_add_subregion(&cregs->component_registers, 0, &cregs->io); > -- > 2.39.2 >