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Tue, 7 May 2024 11:48:47 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id xDo2Bx8VOmYdBAAAD6G6ig (envelope-from ); Tue, 07 May 2024 11:48:47 +0000 Date: Tue, 7 May 2024 13:48:46 +0200 From: Michal Hocko To: Adam Manzanares Cc: "lsf-pc@lists.linux-foundation.org" , "dan.j.williams@intel.com" , "jonathan.cameron@huawei.com" , "dave@stgolabs.net" , Fan Ni , "dave.jiang@intel.com" , "ira.weiny@intel.com" , "alison.schofield@intel.com" , "vishal.l.verma@intel.com" , "gourry.memverge@gmail.com" , "wj28.lee@gmail.com" , "rientjes@google.com" , "ruansy.fnst@fujitsu.com" , "shradha.t@samsung.com" , "mcgrof@kernel.org" , Jim Harris , "linux-mm@kvack.org" , "linux-cxl@vger.kernel.org" , "linux-pci@vger.kernel.org" Subject: Re: [LSF/MM/BPF TOPIC] CXL Development Discussions Message-ID: References: <9bf86b97-319f-4f58-b658-1fe3ed0b1993@nmtadam.samsung> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9bf86b97-319f-4f58-b658-1fe3ed0b1993@nmtadam.samsung> X-Spam-Level: X-Spamd-Result: default: False [-2.30 / 50.00]; BAYES_HAM(-3.00)[100.00%]; SUSPICIOUS_RECIPS(1.50)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_RHS_NOT_FQDN(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FUZZY_BLOCKED(0.00)[rspamd.com]; ARC_NA(0.00)[]; TO_DN_EQ_ADDR_SOME(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RCPT_COUNT_TWELVE(0.00)[20]; MIME_TRACE(0.00)[0:+]; FREEMAIL_ENVRCPT(0.00)[gmail.com]; FREEMAIL_CC(0.00)[lists.linux-foundation.org,intel.com,huawei.com,stgolabs.net,samsung.com,gmail.com,google.com,fujitsu.com,kernel.org,kvack.org,vger.kernel.org]; RCVD_TLS_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; RCVD_VIA_SMTP_AUTH(0.00)[]; TAGGED_RCPT(0.00)[]; MISSING_XM_UA(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,imap1.dmz-prg2.suse.org:rdns] X-Spam-Score: -2.30 X-Spam-Flag: NO On Mon 06-05-24 19:27:10, Adam Manzanares wrote: > Hello all, > > I would like to have a discussion with the CXL development community about > current outstanding issues and also invite developers interested in RAS and > memory tiering to participate. > > The first topic I believe we should discuss is how we can ensure as a group > that we are prioritizing upstream work. On a recent upstream CXL development > discussion call there was a call to review more work. I apologize for not > grabbing the link, but I believe Dave Jiang is leveraging patchwork and this > link should be shared with others so we can help get more reviews where needed. > > The second topic I would like to discuss is how we integrate RAS features that > have similar equivalents in the kernel. A CXL device can provide info about > memory media errors in a similar fashion to memory controllers that have EDAC > support. Discussions have been put on the list and I would like to hear thoughts > from the community about where this should go [1]. On the same topic CXL has > port level RAS features and the PCIe DW series touched on this issue [2] > > The third topic I would like to discuss is how we can get a set of common > benchmarks for memory tiering evaluations. Our team has done some initial > work in this space, but we want to hear more from end users about their > workloads of concern. There was a proposal related to this topic, but from what > I understand no meeting has been held [3]. > > The last topic that I believe is worth discussion is how do we come up with > a baseline for testing. I am aware of 3 efforts that could be used cxl_test, > qemu, and uunit testing framework [4]. This seems to be quite a lot for a single time slot. I think it would make sense to split that into more slots. WDYT? -- Michal Hocko SUSE Labs