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From: Alison Schofield <alison.schofield@intel.com>
To: Foryun Ma <foryun.ma@jaguarmicro.com>
Cc: angus.chen@jaguarmicro.com, dave.jiang@intel.com,
	dave@stgolabs.net, linux-cxl@vger.kernel.org, rrichter@amd.com
Subject: Re: [PATCH v2] cxl/core/pci: Move reading of control register to immediately before usage
Date: Mon, 3 Jun 2024 08:52:32 -0700	[thread overview]
Message-ID: <Zl3mwH0kGEiDatp9@aschofie-mobl2> (raw)
In-Reply-To: <20240530064751.586-1-foryun.ma@jaguarmicro.com>

On Thu, May 30, 2024 at 02:47:51PM +0800, Foryun Ma wrote:
> Relocate the reading of the DVSEC control register to immediately
> before usage and avoid unnecessary PCI config access from the read
> if DVSEC capability check, hdm_count check, or device validity check
> results in failure.
> 
> Signed-off-by: Foryun Ma <foryun.ma@jaguarmicro.com>
> 
> V1->V2: change the subject and commit log, suggested by dave.jiang
> 	and add change log, suggested by Alison Schofield
> ---

I see the value in this patch as a cleanup because despite what a
reader well versed in this area might know (PCI config cycles are
cheap and these failure conditions are unlikely) the code breaks
a basic pattern - read then check, don't read, then check later.
You calling attention to it makes all of us better reviewers, and
if we don't fix it now we may see this patch again from another 
reader.

If you want to continue the submittal, please do:
- incorporate my feedback from v1: move the check to after the comment
- Post a v3 as a new message, not in reply to this message.

With that, I'll offer my Reviewed-by tag and this can be considered
for upstream merge.

-- Alison







>  drivers/cxl/core/pci.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 8567dd11eaac..627be83881e9 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -338,10 +338,6 @@ int cxl_dvsec_rr_decode(struct device *dev, int d,
>  	if (rc)
>  		return rc;
>  
> -	rc = pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl);
> -	if (rc)
> -		return rc;
> -
>  	if (!(cap & CXL_DVSEC_MEM_CAPABLE)) {
>  		dev_dbg(dev, "Not MEM Capable\n");
>  		return -ENXIO;
> @@ -363,6 +359,10 @@ int cxl_dvsec_rr_decode(struct device *dev, int d,
>  		return rc;
>  	}
>  
> +	rc = pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl);
> +	if (rc)
> +		return rc;
> +
>  	/*
>  	 * The current DVSEC values are moot if the memory capability is
>  	 * disabled, and they will remain moot after the HDM Decoder
> -- 
> 2.34.1
> 

      parent reply	other threads:[~2024-06-03 15:52 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-30  1:32 [PATCH] cxl/core/pci: Move reading of control register to immediately before usage Foryun Ma
2024-05-30  3:43 ` Alison Schofield
2024-05-30  6:47   ` [PATCH v2] " Foryun Ma
2024-05-31 15:31     ` Dan Williams
2024-06-03 15:52     ` Alison Schofield [this message]

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