From: Alison Schofield <alison.schofield@intel.com>
To: Foryun Ma <foryun.ma@jaguarmicro.com>
Cc: dan.j.williams@intel.com, angus.chen@jaguarmicro.com,
dave.jiang@intel.com, dave@stgolabs.net,
linux-cxl@vger.kernel.org, rrichter@amd.com
Subject: Re: [PATCH v3] cxl/core/pci: Move reading of control register to immediately before usage
Date: Wed, 5 Jun 2024 08:35:23 -0700 [thread overview]
Message-ID: <ZmCFu0US7IBuPCk2@aschofie-mobl2> (raw)
In-Reply-To: <20240604032151.655-1-foryun.ma@jaguarmicro.com>
On Tue, Jun 04, 2024 at 11:21:51AM +0800, Foryun Ma wrote:
> Relocate the reading of the DVSEC control register to immediately
> before usage and avoid unnecessary PCI config access from the read
> if DVSEC capability check, hdm_count check, or device validity check
> results in failure.
>
> Signed-off-by: Foryun Ma <foryun.ma@jaguarmicro.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
prev parent reply other threads:[~2024-06-05 15:35 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-04 3:21 [PATCH v3] cxl/core/pci: Move reading of control register to immediately before usage Foryun Ma
2024-06-05 12:15 ` Jonathan Cameron
2024-06-05 15:35 ` Alison Schofield [this message]
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