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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6bb3fac10e3sm10707486d6.109.2024.07.25.15.00.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jul 2024 15:00:06 -0700 (PDT) Date: Thu, 25 Jul 2024 18:00:00 -0400 From: Gregory Price To: Robert Richter Cc: Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Cameron , Dave Jiang , Davidlohr Bueso , linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 0/5] Address translation for HDM decoding Message-ID: References: <20240701174754.967954-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240701174754.967954-1-rrichter@amd.com> On Mon, Jul 01, 2024 at 07:47:48PM +0200, Robert Richter wrote: > Default expectation of Linux is that HPA == SPA, which means that > hardware addresses in the decoders are the same as the kernel sees > them. However, there are platforms where this is not the case and an > address translation between decoder's (HPA) and the system's physical > addresses (SPA) is needed. > > This series implements address translation for HDM decoding. The > implementation follows the rule that the representation of hardware > address ranges in the kernel are all SPA. If decoder registers (HDM > decoder cap or register range) are not SPA, a base offset must be > applied. Translation happens when accessing the registers back and > forth. After a read access an address will be converted to SPA and > before a write access the programmed address is translated from an > SPA. The decoder register access can be easily encapsulated by address > translation and thus there are only a few places where translation is > needed and the code must be changed. This is implemented in patch #2, > patch #1 is a prerequisite. > > Address translation is restricted to platforms that need it. As such a > platform check is needed and a flag is introduced for this (patch #3). > > For address translation the base offset must be determined for the > memory domain. Depending on the platform there are various options for > this. The address range in the CEDT's CFWMS entry of the CXL host > bridge can be used to determine the decoder's base address (patch > #4). This is enabled for AMD Zen4 platforms (patch #5). > > Changelog: > > v2: > * Fixed build error for other archs [kbot] > Hi Robert, I'm looking to test this patch series but saw you were looking at reworking a portion of it. Just wanted to inquire as to whether you think I should wait for a v3 given this is a few weeks old now. Thanks! ~Gregory