[PATCH v2 15/15] efx: support pio mapping based on cxl

alejandro.lucero-palau
2024-07-15T17:29:11Z

From: Alejandro Lucero <alucerop@amd.com>

With a device supporting CXL and successfully initialised, use the cxl
region to map the memory range and use this mapping for PIO buffers.

Signed-off-by: Alejandro Lucero <alucerop@amd.com>
---
drivers/net/ethernet/sfc/ef10.c | 25 +++++++++++++++++++++----
drivers/net/ethernet/sfc/efx_cxl.c | 12 +++++++++++-
drivers/net/ethernet/sfc/mcdi_pcol.h | 3 +++
drivers/net/ethernet/sfc/nic.h | 1 +
4 files changed, 36 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/sfc/ef10.c b/drivers/net/ethernet/sfc/ef10.c
index 8fa6c0e9195b..3924076d2628 100644
--- a/drivers/net/ethernet/sfc/ef10.c
+++ b/drivers/net/ethernet/sfc/ef10.c
@@ -24,6 +24,7 @@
#include <linux/wait.h>
#include <linux/workqueue.h>
#include <net/udp_tunnel.h>
+#include "efx_cxl.h"

/* Hardware control for EF10 architecture including 'Huntington'. */

@@ -177,6 +178,12 @@ static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
efx->num_mac_stats);
}

+ if (outlen < MC_CMD_GET_CAPABILITIES_V7_OUT_LEN)
+ nic_data->datapath_caps3 = 0;
+ else
+ nic_data->datapath_caps3 = MCDI_DWORD(outbuf,
+ GET_CAPABILITIES_V7_OUT_FLAGS3);
+
return 0;
}

@@ -1275,10 +1282,20 @@ static int efx_ef10_dimension_resources(struct efx_nic *efx)
return -ENOMEM;
}
nic_data->pio_write_vi_base = pio_write_vi_base;
- nic_data->pio_write_base =
- nic_data->wc_membase +
- (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF -
- uc_mem_map_size);
+
+ if ((nic_data->datapath_caps3 &
+ (1 << MC_CMD_GET_CAPABILITIES_V10_OUT_CXL_CONFIG_ENABLE_LBN)) &&
+ efx->cxl->ctpio_cxl)
+ {
+ nic_data->pio_write_base =
+ efx->cxl->ctpio_cxl +
+ (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF -
+ uc_mem_map_size);
+ } else {
+ nic_data->pio_write_base =nic_data->wc_membase +
+ (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF -
+ uc_mem_map_size);
+ }

rc = efx_ef10_link_piobufs(efx);
if (rc)
diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
index 4012e3faa298..8e65ef42a572 100644
--- a/drivers/net/ethernet/sfc/efx_cxl.c
+++ b/drivers/net/ethernet/sfc/efx_cxl.c
@@ -21,8 +21,8 @@
void efx_cxl_init(struct efx_nic *efx)
{
struct pci_dev *pci_dev = efx->pci_dev;
+ resource_size_t start, end, max = 0;
struct efx_cxl *cxl = efx->cxl;
- resource_size_t max = 0;
struct resource res;
u16 dvsec;

@@ -104,6 +104,13 @@ void efx_cxl_init(struct efx_nic *efx)
return;
}

+ cxl_accel_get_region_params(cxl->efx_region, &start, &end);
+
+ cxl->ctpio_cxl = ioremap(start, end - start);
+ if (!cxl->ctpio_cxl) {
+ pci_info(pci_dev, "CXL accel create region failed");
+ cxl_dpa_free(cxl->cxled);
+ }
out:
cxl_release_endpoint(cxl->cxlmd, cxl->endpoint);
}
@@ -112,6 +119,9 @@ void efx_cxl_exit(struct efx_nic *efx)
{
struct efx_cxl *cxl = efx->cxl;

+ if (cxl->ctpio_cxl)
+ iounmap(cxl->ctpio_cxl);
+
if (cxl->efx_region)
cxl_region_detach(cxl->cxled);

diff --git a/drivers/net/ethernet/sfc/mcdi_pcol.h b/drivers/net/ethernet/sfc/mcdi_pcol.h
index cd297e19cddc..05fd5e021142 100644
--- a/drivers/net/ethernet/sfc/mcdi_pcol.h
+++ b/drivers/net/ethernet/sfc/mcdi_pcol.h
@@ -18374,6 +18374,9 @@
#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148
#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14
#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_CXL_CONFIG_ENABLE_OFST 148
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_CXL_CONFIG_ENABLE_LBN 16
+#define MC_CMD_GET_CAPABILITIES_V10_OUT_CXL_CONFIG_ENABLE_WIDTH 1
/* These bits are reserved for communicating test-specific capabilities to
* host-side test software. All production drivers should treat this field as
* opaque.
diff --git a/drivers/net/ethernet/sfc/nic.h b/drivers/net/ethernet/sfc/nic.h
index 1db64fc6e909..cd635f4f7f94 100644
--- a/drivers/net/ethernet/sfc/nic.h
+++ b/drivers/net/ethernet/sfc/nic.h
@@ -186,6 +186,7 @@ struct efx_ef10_nic_data {
bool must_check_datapath_caps;
u32 datapath_caps;
u32 datapath_caps2;
+ u32 datapath_caps3;
unsigned int rx_dpcpu_fw_id;
unsigned int tx_dpcpu_fw_id;
bool must_probe_vswitching;
--
2.17.1